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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002. all rights reserved. aduc831 features analog i/o 8-channel, 247 ksps 12-bit adc dc performance: 1 lsb inl ac performance: 71 db snr dma controller for high speed adc-to-ram capture 2 12-bit (monotonic) voltage output dacs dual output pwm/ - dacs on-chip temperature sensor function 3 c on-chip voltage reference memory 62 kbytes on-chip flash/ee program memory 4 kbytes on-chip flash/ee data memory flash/ee, 100 yr retention, 100 kcycles endurance 2304 bytes on-chip data ram 8051 based core 8051 compatible instruction set (16 mhz max) 12 interrupt sources, 2 priority levels dual data pointer extended 11-bit stack pointer on-chip peripherals time interval counter (tic) uart, i 2 c , and spi serial i/o watchdog timer (wdt), power supply monitor (psm) power specified for 3 v and 5 v operation normal, idle, and power-down modes power-down: 20 a @ 3 v applications optical networking?aser power control base station systems precision instrumentation, smart sensors transient capture systems das and communications systems pin compatible upgrade to existing aduc812 systems that require additional code or data memory. runs from 1 mhz?6 mhz to external crystal. the aduc832 is also available. functionally is the same as the aduc831, except the aduc832 runs from a 32 khz external crystal with on-chip pll. microconverter is a registered tr ademark and qui ckstart is a trademark of analog devices, inc. spi is a registered trademark of motorola, inc. i 2 c is a registered trademark of philips corporation. general description the aduc831 is a fully integrated 247 ksps data acquisition system incorporating a high performance self-calibrating multi- channel 12-bit adc, dual 12-bit dacs, and programmable 8-bit mcu on a single chip. the microcontroller core is an 8052, and therefore 8051- instruction-set compatible with 12 core clock periods per machine cycle. 62 kbytes of nonvolatile flash/ee program memory are provided on-chip. four kbytes of nonvolatile flash/ee data memory, 256 bytes ram and 2 kbytes of extended ram are also integrated on-chip. the aduc831 also incorporates additional analog functionality with two 12-bit dacs, power supply monitor, and a band gap reference. on-chip digital peripherals include two 16-bit - ? dacs, dual output 16-bit pwm, watchdog timer, time interval counter, three timers/counters, timer 3 for baud rate generation and serial i/o ports (i 2 c, spi and uart). on-chip factory firmware supports in-circuit serial download and debug modes (via uart), as well as single-pin emulation mode via the ea pin. the aduc831 is supported by quickstart and quickstart plus development systems featuring low cost software and hardware development tools. a functional block diagram of the aduc831 is shown above with a more detailed block diagram shown in figure 1. the part is specified for 3 v and 5 v operation over the extended industrial temperature range, and is available in a 52-lead plastic quad flatpack package and in a 56-lead chip scale package. functional block diagram 62 kbytes flash/ee program memory 4 kbytes flash/ee data memory 2304 bytes user ram 3 16 bit timers 1 real time clock parallel ports 8051-based mcu with additional peripherals aduc831 xtal2 xtal1 temp sensor v ref internal band gap vref adc0 adc1 adc5 adc6 adc7 osc 12-bit dac dac pwm0 t/h mux 12-bit adc hardware calibraton buf dac buf pwm1 12-bit dac 16-bit - dac 16-bit - dac 16-bit pwm 16-bit pwm power supply mon watchdog timer uart, i 2 c, and spi serial i/o mux microconverter , 12-bit adcs and dacs with embedded 62 kbytes flash mcu
rev. 0 e2e aduc831 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . 7 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . 9 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance characteristics . . 11 memory organization . . . . . . . . . . . . . . . . . . . 14 overview of mcu-related sfrs . . . . . . . . . . 15 accumulator sfr (acc) . . . . . . . . . . . . . . . . . . . . . . . . . 15 b sfr (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 stack pointer sfr (sp and sph) . . . . . . . . . . . . . . . . . 15 data pointer (dptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program status word sfr (psw) . . . . . . . . . . . . . . . . . . 16 power control sfr (pcon) . . . . . . . . . . . . . . . . . . . . . . 16 special function registers . . . . . . . . . . . . . . 17 adc circuit information . . . . . . . . . . . . . . . . 18 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . 18 typical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adccon1 e (adc control sfr #1) . . . . . . . . . . . . . . 19 adccon2 e (adc control sfr #2) . . . . . . . . . . . . . . 20 adccon3 e (adc control sfr #3) . . . . . . . . . . . . . . 21 driving the a/d converter . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage reference connections . . . . . . . . . . . . . . . . . . . . 23 configuring the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 adc dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 micro operation during adc dma mode . . . . . . . . . . . 25 adc offset and gain calibration coefficients . . . . . . . . 25 calibrating the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 nonvolatile flash memory . . . . . . . . . . . . . . 27 flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . 27 flash/ee memory and the aduc831 . . . . . . . . . . . . . . . 27 aduc831 flash/ee memory reliability . . . . . . . . . . . . . 27 using the flash/ee program memory . . . . . . . . . . . . . . . 28 uload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 flash/ee program memory security . . . . . . . . . . . . . . . . 28 using the flash/ee data memory . . . . . . . . . . . . . . . . . . 29 econ?flash/ee memory control sfr . . . . . . . . . . . . 29 flash/ee memory timing . . . . . . . . . . . . . . . . . . . . . . . . 30 aduc831 configuration register (cfg831) . . 31 user interface to other on-chip aduc831 peripherals . . . . . . . . . . . . . . . . . . . . . 32 using the dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pulsewidth modulator (pwm) . . . . . . . . . . . . . . . . . . . . . 35 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . 38 i 2 c compatible interface . . . . . . . . . . . . . . . . . . . . . . . . . 40 dual data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 timer interval counter . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8052 compatible on-chip peripherals . . . . 47 parallel i/o ports 0e3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 uart serial port control register . . . . . . . . . . . . . . . . . 55 uart operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 56 uart serial port baud rate generation . . . . . . . . . . . . 56 timer 1 generated baud rates . . . . . . . . . . . . . . . . . . . . 57 timer 2 generated baud rates . . . . . . . . . . . . . . . . . . . . 57 timer 3 generated baud rates . . . . . . . . . . . . . . . . . . . . 58 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 aduc831 hardware design considerations 60 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 external memory interface . . . . . . . . . . . . . . . . . . . . . . . 60 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 grounding and board layout recommendations . . . . . . 63 other hardware considerations . . . . . . . . 63 in-circuit serial download access . . . . . . . . . . . . . . . . . 63 embedded serial port debugger . . . . . . . . . . . . . . . . . . . 64 single-pin emulation mode . . . . . . . . . . . . . . . . . . . . . . . 64 typical system configuration . . . . . . . . . . . . . . . . . . . . . 64 development tools . . . . . . . . . . . . . . . . . . . . . . 65 timing specifications . . . . . . . . . . . . . . . . . . . . 66 outline dimensions . . . . . . . . . . . . . . . . . . . . . . 76
rev. 0 e3e parameter v dd = 5 v v dd = 3 v unit test conditions/comments adc channel specifications dc accuracy 2, 3 f sample = 147 khz, see page 11 for typical performance at other f sample resolution 12 12 bits integral nonlinearity 1 1l sb max 2.5 v internal reference 0.3 0.3 lsb typ differential nonlinearity 0.9 0.9 lsb max 2.5 v internal reference 0.25 0.25 lsb typ integral nonlinearity 4 1.5 1.5 lsb max 1 v external reference differential nonlinearity 4 +1.5/-0.9 +1.5/e0.9 lsb max 1 v external reference code distribution 1 1 lsb typ adc input is a dc voltage calibrated endpoint errors 5, 6 offset error 4 4lsb max offset error match 1 1lsb typ gain error 2 3lsb max gain error match e85 e85 db typ dynamic performance f in = 10 khz sine wave f sample = 147 khz signal-to-noise ratio (snr) 7 71 71 db typ total harmonic distortion (thd) e85 e85 db typ peak harmonic or spurious noise e85 e85 db typ channel-to-channel crosstalk 8 e80 e80 db typ analog input input voltage ranges 0 to v ref 0 to v ref v leakage current 1 1 a max input capacitance 32 32 pf typ temperature sensor 9 voltage output at 25 c 650 650 mv typ voltage tc e2.0 e2.0 mv/ c typ accuracy 3 3 c typ internal 2.5 v v ref 1.5 1.5 c typ external 2.5 v v ref dac channel specifications dac load to agnd internal buffer enabled r l = 10 k , c l = 100 pf dc accuracy 10 resolution 12 12 bits relative accuracy 3 3lsb typ differential nonlinearity 11 e1 e1 lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 50 50 mv max v ref range gain error 1 1% maxav dd range 1 1% typ v ref range gain error mismatch 0.5 0.5 % typ % of full scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ dac v ref = 2.5 v voltage range_1 0 to v dd 0 to v dd v typ dac v ref = v dd output impedance 0.5 0.5 typ dac ac characteristics voltage output settling time 15 15 s typ full-scale settling time to within 1/2 lsb of final value digital-to-analog glitch energy 10 10 nv sec typ 1 lsb change at major carry (av dd = dv dd = 2.7 v to 3.3 v or 4.5 v to 5.5 v. v ref = 2.5 v internal reference, mclkin = 16 mhz, all specifications t a = t min to t max , unless otherwise noted.) specifications 1 aduc831
rev. 0 C4C aduc831 parameter v dd = 5 v v dd = 3 v unit test conditions/comments dac channel specifications 12, 13 internal buffer disabled dc accuracy 10 resolution 12 12 bits relative accuracy 3 3lsb typ differential nonlinearity 11 ? ? lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 5 5 mv max v ref range gain error ?.3 ?.3 % typ v ref range gain error mismatch 4 0.5 0.5 % max % of full-scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ dac v ref = 2.5 v reference input/output reference output 14 output voltage (v ref ) 2.5 2.5 v accuracy 2.5 2.5 % max of v ref measured at the c ref pin power supply rejection 47 57 db typ reference temperature coefficient 100 100 ppm/ c typ internal v ref power-on time 80 80 ms typ external reference input 15 voltage range (v ref ) 4 0.1 0.1 v min v ref and c ref pins shorted v dd v dd v max input impedance 20 20 k w typ input leakage 1 1 m a max internal band gap deselected via adccon1.6 power supply monitor (psm) dv dd trip point selection range 2.63 v min four trip points selectable in 4. 37 v max this range programmed via tpd1? in psmcon dv dd power supply trip point accuracy 3.5 % max watchdog timer (wdt) 4 time-out period 0 0 ms min nine time-out periods 2000 2000 ms max selectable in this range flash/ee memory reliability characteristics 16 endurance 17 100,000 100,000 cycles min data retention 18 100 100 years min digital inputs input high voltage (v inh ) 4 2.4 2 v min input low voltage (v inl ) 4 0.8 0.4 v max input leakage current (port 0, ea) 10 10 m a max v in = 0 v or v dd 1 1 m a typ v in = 0 v or v dd logic 1 input current (all digital inputs) 10 10 m a max v in = v dd 1 1 m a typ v in = v dd logic 0 input current (port 1, 2, 3) ?5 ?5 m a max ?0 ?5 m a typ v il = 450 mv logic 1-0 transition current (port 2, 3) ?60 ?50 m a max v il = 2 v ?00 ?40 m a typ v il = 2 v specifications (continued)
rev. 0 aduc831 e5e parameter v dd = 5 v v dd = 3 v unit test conditions/comments sclock and reset only 4 (schmitt-triggered inputs) v t+ 1.3 0.95 v min 3.0 2.5 v max v te 0.8 0.4 v min 1.4 1.1 v max v t+ e v te 0.3 0.3 v min 0.85 0.85 v max crystal oscillator logic inputs, xtal1 only v inl , input low voltage 0.8 0.4 v typ v inh , input high voltage 3.5 2.5 v typ xtal1 input capacitance 18 18 pf typ xtal2 output capacitance 18 18 pf typ mcu clock rate 16 16 mhz max digital outputs output high voltage (v oh ) 2.4 v min v dd = 4.5 v to 5.5 v 4.0 v typ i source = 80 a 2.4 v min v dd = 2.7 v to 3.3 v 2.6 v typ i source = 20 a output low voltage (v ol ) ale, ports 0 and 2 0.4 0.4 v max i sink = 1.6 ma 0.2 0.2 v typ i sink = 1.6 ma port 3 0.4 0.4 v max i sink = 4 ma sclock/sdata 0.4 0.4 v max i sink = 8 ma, i 2 c enabled floating state leakage current 4 10 10 a max 1 1 a typ floating state output capacitance 10 10 pf typ start up time mclkin = 16 mhz at power-on 500 500 ms typ from idle mode 100 100 s typ from power-down mode wakeup with int0 i 10 00 wspii ci 10 00 wereset 10 00 aeresetn 0 0 awdtrn cwdconsr
rev. 0 e6e aduc831 notes 1 temperature range e40?c to +125?c. 2 adc linearity is guaranteed during normal micro converter core operation. 3 adc lsb size = v ref /2 12 i.e., for internal v ref = 2.5 v, 1 lsb = 610
rev. 0 aduc831 e7e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the aduc831 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description option aduc831bs e40 c to +125 c 52-lead plastic quad flatpack s-52 ADUC831BCP e40 c to +85 c 56-lead chip scale package cp-56 eval-aduc831qs q uickstart development system eval-aduc831qsp quickstart plus development system absolute maximum ratings * (t a = 25 c unless otherwise noted.) av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v dv dd to dgnd, av dd to agnd . . . . . . . . . e0.3 v to +7 v digital input voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . e0.3 v to dv dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . e0.3 v to av dd + 0.3 v analog inputs to agnd . . . . . . . . . . e0.3 v to av dd + 0.3 v operating temperature range industrial aduc831bs . . . . . . . . . . . . . . . . . . . . . . e40 c to +125 c operating temperature range industrial ADUC831BCP . . . . . . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance (aduc831bs) . . . . . . . . . . 90 c/w ja thermal impedance (ADUC831BCP) . . . . . . . . . 52 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
rev. 0 C8C aduc831 pin configuration watchdog timer 256 bytes user ram power supply monitor temp sensor band gap reference av dd agnd dv dd dv dd dv dd dgnd dgnd dgnd reset por sdata\mosi miso ss xtal1 aduc831 adc control and calibration dac1 dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale single-pin emulator txd rxd 4 kbytes data flash/ee 62 kbytes program flash/ee including user download mode asynchronous serial port ( uart) 8052 mcu core downloader debugger synchronous serial interface (i 2 c and spi ) 16-bit counter timers time interval counter ( wakeup cct) xtal2 osc 2 kbytes user xram 2 data pointers 11-bit stack pointer 12-bit voltage output dac mux ... ... 12-bit adc adc0 adc1 adc6 adc7 dac0 mux 16-bit - dac pwm0 pwm1 16-bit pwm 16-bit pwm pwm control 16-bit - dac t/h v ref c ref buf uart timer sclock figure 1. aduc831 block diagram (shaded areas are features not present on the aduc812) p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd av dd agnd agnd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 p.7/adc7 reset p3.0/rxd p3.1/txd p3.2/ int0 p3.3/ int1 /miso/pwm1 dv dd dgnd p3.4/t0/pwmc/pwm0 p3.5/t1/ convst p3.6/ wr p3.7/ rd sclock p2.7/a15/a23 p2.6/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dgnd dv dd xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi p1.0/adc0/t2 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea 14 1 2 3 4 5 6 7 8 9 10 11 13 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 45 46 47 48 49 50 51 52 53 54 55 56 pin 1 identifier 44 aduc831 56-lead csp top view (not to scale) xtal2 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 aduc831 52-lead pqfp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea p1.7/adc7 reset p3.0/rxd p3.1/txd p3.2/ int0 p3.3/ int1 /miso/pwm0 dv dd p3.4/t0/pwmc/pwm1 p3.5/t1/ convst p3.6/ wr p3.7/ rd sclock p1.0/adc0/t2 p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd a gnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 p2.7/pwm1/a15/a23 p2.6/pwm0/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dv dd xtal2 xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi dgnd
rev. 0 aduc831 e9e pin function descriptions mnemonic type function dv dd pd igital positive supply voltage, 3 v or 5 v nominal av dd pa nalog positive supply voltage, 3 v or 5 v nominal c ref id ecoupling input for on-chip reference. connect 0.1 f between this pin and agnd. v ref i/o reference input/output. this pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. the nominal internal reference voltage is 2.5 v and this appears at the pin. this pin can be overdriven by an external reference. agnd g analog ground. ground reference point for the analog circuitry. p1.0ep1.7 i port 1 is an 8-bit input port only. unlike other ports, port 1 defaults to analog input mode, to configure any of these port pins as a digital input, write a 0 to the port bit. port 1 pins are multifunction and share the following functionality. adc0eadc7 i analog inputs. eight single-ended analog inputs. channel selection is via adccon2 sfr. t2 i timer 2 digital input. input to timer/counter 2. when enabled, counter 2 is incremented in response to a 1-to-0 transition of the t2 input. t2ex i digital input. capture/reload trigger for counter 2 and also functions as an up/down control input for counter 2. ss i ssispii sdata io si ccspidiop scoc io scpi ccspisic osi io spiosidiopspii iso io spiisodiopspisi dac0 o vodac0 dac1 o vodac1 reset i dia p0p io pp1 ap p pwc i pwci pw0 o pw0vopw pw1 o pw1vosc1r rd io rdia)dios)sart)p td o tdoa)cos)sart)p int0 i i0i tt 0 int1 i i1i tt 1 t0 i tc0i t1 i tc1i convst i acsiadcecse a wr ow csop0 rd or csoep0 ta o oioa ta1 i iioa dnd d p0p io pp1 aa1) ap a1a) p
rev. 0 e10e aduc831 terminology adc specifications integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 lsb. gain error this is the deviation of the last code transition from the ideal ain voltage (full scale e 1.5 lsb) after the offset error has been adjusted out. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fun- damental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to(noise distortion)= (6.02n + 1.76) db + thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion is the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endp oints of the dac transfer function. it is measured after adjusting for zero error and full-scale error. voltage output settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is specified as the area of the glitch in nv sec. pin function descriptions (continued) mnemonic type function psen op seot i t psen reset ae o aeot )i ea ie aeiw 00001w t p0p00 io p 0odiop01 a0a) p0 i 1
rev. 0 t ypical performance characteristicseaduc831 e11e the typical performance plots presented in this section illustrate typical performance of the aduc831 under various operating conditions. tpc 1 and tpc 2 below show typical adc integral nonlinearity (inl) errors from adc code 0 to code 4095 at 5 v and 3 v supplies respectively. the adc is using its internal reference (2.5 v) and operating at a sampling rate of 152 khz and the typically worst-case errors in both plots is just less than 0.3 lsbs. tpc 3 and tpc 4 below show the variation in worst case positive (wcp) inl and worst case negative (wcn) inl versus external reference input voltage. tpc 5 and tpc 6 show typical adc differential nonlinearity (dnl) errors from adc code 0 to code 4095 at 5 v and 3 v sup- plies, respectively. the adc is using its internal reference (2. v) and operating at a sampling rate of 152 khz and the typically worst case errors in both plots is just less than 0.2 lsbs. tpc 7 and tpc 8 show the variation in worst case positive (wcp) dnl and worst-case negative (wcn) dnl versus external reference input voltage. tpc 9 shows a histogram plot of 10,000 adc conversion results on a dc input with v dd = 5 v. the plot illustrates an excellent code distribution pointing to the low noise perfor- mance of the on-chip precision adc. tpc 10 shows a histogram plot of 10,000 adc conversion results on a dc input for v dd = 3 v. the plot again illustrates a very tight code distribution of 1 lsb with the majority of codes appearing in one output bin. tpc 11 and tpc 12 show typical fft plots for the aduc831. these plots were generated using an external clock input. the adc is using its internal reference (2.5 v) sampling a full-scale, 10 khz sine wave test tone input at a sampling rate of 149.79 khz. the resultant ffts shown at 5 v and 3 v supplies illustrate an excellent 100 db noise floor, 71 db signal-to-noise ratio (snr) and thd greater than e80 db. tpc 13 and tpc 14 show typical dynamic performance versus external reference voltages. again excellent ac performance can be observed in both plots with some roll-off being observed as v ref falls below 1 v. tpc 15 shows typical dynamic performance versus sampling frequency. snr levels of 71 dbs are obtained across the sam- pling range of the aduc831. tpc 16 shows the voltage output of the on-chip temperature sensor versus temperature. although the initial voltage output at 25?c can vary from part to part, the resulting slope of e2 mv/?c is constant across all parts. adc codes e1.0 0 511 lsbs 1023 2047 2559 3071 e0.8 1535 3583 e0.6 e0.4 e0.2 0 0.2 0.4 0.6 0.8 1.0 av dd / dv dd = 5v f s = 152khz 4095 tpc 1. typical inl error, v dd = 5 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz tpc 2. typical inl error, v dd = 3 v external reference e v 1.2 wcpeinl e lsbs 0.8 0.4 0 e0.4 e0.6 1.0 0.6 0.2 e0.2 av dd /dv dd = 5v f s = 152khz 0.5 1.0 1.5 2.0 2.5 5.0 0.6 0.4 0 e0.4 e0.6 0.2 e0.2 wcneinl e lsbs wcn inl wcp inl tpc 3. typical worst case inl error vs. v ref, v dd = 5 v external reference e v wcpeinl e lsbs 0.8 0.4 0 e0.4 e0.8 0.6 0.2 e0.2 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 wcneinl e lsbs e0.6 0.8 0.4 0 e0.4 e0.8 0.6 0.2 e0.2 e0.6 3.0 2.0 1.0 wcn inl wcp inl tpc 4. typical worst case inl error vs. v ref, v dd = 3 v
rev. 0 e12e aduc831 adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 5v f s = 152khz tpc 5. typical dnl error, v dd = 5 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz tpc 6. typical dnl error, v dd = 3 v external reference e v e0.6 0.5 wcpednl e lsbs 1.0 2.0 2.5 5.0 e0.4 1.5 e0.2 0 0.2 0.4 0.6 wcnednl e lsbs e0.4 e0.6 e0.2 0 0.2 0.4 0.6 av dd / dv dd = 5v f s = 152khz wcp dnl wcn dnl tpc 7. typical worst case dnl error vs. v ref , v dd = 5 v external reference e v wcpednl e lsbs 0.7 0.5 0.1 e0.5 e0.7 0.3 e0.3 av dd /dv dd = 3v f s = 152khz 0.5 1.0 1.5 2.0 2.5 3.0 wcnednl e lsbs wcp dnl wcn dnl e0.1 0.7 0.5 0.1 e0.5 e0.7 0.3 e0.3 e0.1 tpc 8. typical worst case dnl error vs. v ref, v dd = 3 v code 817 818 819 820 821 10000 occurrence 8000 6000 4000 2000 0 tpc 9. code histogram plot, v dd = 5 v code 10000 817 818 819 820 821 occurrence 8000 6000 4000 2000 0 9000 7000 5000 3000 1000 tpc 10. code histogram plot, v dd = 3 v
rev. 0 aduc831 e13e frequency e khz 010 dbs 20 40 50 60 e160 30 70 e140 e120 e100 e80 e60 e40 e20 0 20 av dd / dv dd = 5v f s = 152khz f in = 9.910khz snr = 71.3db thd = e88.0db enob = 11.6 tpc 11. dynamic performance at v dd = 5 v frequency e khz 010 dbs 20 40 50 60 e160 30 70 e140 e120 e100 e80 e60 e40 e20 0 20 av dd / dv dd = 3v f s = 149.79khz f in = 9.910khz snr = 71.0db thd = e83.0db enob = 11.5 tpc 12. dynamic performance at v dd = 3 v external reference e v 50 0.5 snr e dbs 1.0 2.0 2.5 5.0 55 1.5 60 65 70 75 80 thd e dbs e100 e95 e90 e85 e80 e75 e70 av dd / dv dd = 5v f s = 152khz snr thd tpc 13. typical dynamic performance vs. v ref, v dd = 5 v external reference e v snr e dbs 80 75 65 50 70 55 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 thd e dbs snr thd 60 e70 e75 e85 e100 e80 e95 e90 1.0 2.0 3.0 tpc 14. typical dynamic performance vs. v ref, v dd = 3 v frequency e khz 64 92.262 snr e dbs 119.05 172.62 199.41 226.19 66 145.83 68 70 72 76 80 av dd / dv dd = 5v 78 74 62 60 65.476 tpc 15. typical dynamic performance vs. sampling frequency temperature e c 0.40 e40 voltage e v e20 0.45 0.50 0.55 0.60 0.70 0.80 0.75 0.65 av dd / dv dd = 3v slope = 2mv/ c 0 25 50 85 tpc 16. typical temperature sensor output vs. temperature
rev. 0 e14e aduc831 memory organization the aduc831 contains four different memory blocks: ? 62 kbytes of on-chip flash/ee program memory ? 4 kbytes of on-chip flash/ee data memory ? 256 bytes of general-purpose ram ? 2 kbytes of internal xram flash/ee program memory the aduc831 provides 62 kbytes of flash/ee program memory to run user code. the user can choose to run code from this internal memory or run code from an external program memory. if the user applies power or resets the device while the ea ee adc1 pc 1adc1 00 i000 nop tart t ee eed eed srsr)a ee ee pra tra 1rat 1ra t1ra sr t1 t r0rt 11)0 00t 0 r0 0 r0)1t ra itaddressae itaddresses) oransoeit reisters r0r ans seected via itsinpsw 11 10 01 00 0 0 1 1 00 0 10 1 0 resetvaeo stacpointer 0 eneraprpose area 1id tadc10ra 1 11 0 00 rao adc1c 1) 11i ra0100ra t11spspsr tspsr10t spsrtssr 11 pper1 teso oncipra datastac oresp1 dataon oresp0) ower teso oncipra dataon) 00 0 teso oncipdata ra data stac) 00 c10 c11 100 espo
rev. 0 aduc831 e15e external data memory (external xram) just like a standard 8051 compatible core, the aduc831 can access external data memory using a movx instruction. the movx instruction automatically outputs the various control strobes required to access the data memory. the aduc831, however, can access up to 16 mbytes of external data memory. this is an enhancement of the 64 kbytes external data memory space available on a standard 8051 compatible core. the external data memory is discussed in more detail in the aduc831 hardware design considerations section. internal xram 2 kbytes of on-chip data memory exist on the aduc831. this memory, although on-chip, is also accessed via the movx instruction. the 2 kbytes of internal xram are mapped into the bottom 2 kbytes of the external address space if the cfg831 bit is set. otherwise, access to the external data memory will occur just like a standard 8051. when using the internal xram, ports 0 and 2 are free to be used as general-purpose i/o. external data memory space (24-bit address space) 000000h ffffffh cfg831.0 = 0 external data memory space (24-bit address space) 000000h ffffffh cfg831.0 = 1 0007ffh 000800h 2 kbytes on-chip xram figure 4. internal and external xram special function registers (sfrs) the sfr space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. it provides an interface between the cpu and all on-chip periph- erals. a block diagram showing the programming model of the aduc831 via the sfr area is shown in figure 5. all registers, except the program counter (pc) and the four general-purpose register banks, reside in the sfr area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and all on-chip peripherals. 128-byte special function register area 62-kbyte electrically reprogrammable nonvolatile flash/ee program memory 8051- compatible core other on-chip peripherals temperature sensor 2 12-bit dacs serial i/o wdt psm tic 8-channel 12-bit adc 4-kbyte electrically reprogrammable nonvolatile flash/ee data memory 2304 bytes ram figure 5. programming model accumulator sfr (acc) acc is the accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and boolean bit manipulations. the mnemonics for accumulator-specific instructions refer to the accumulator as a. b sfr (b) the b register is used with the acc for multiplication and division operations. for other instructions it can be treated as a general-purpose scratchpad register. stack pointer (sp and sph) the sp sfr is the stack pointer and is used to hold an internal ram address that is called the top of the stack . the sp register is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the sp register is initialized to 07h after a reset. this causes the stack to begin at location 08h. as mentioned earlier, the aduc831 offers an extended 11-bit stack pointer. the three extra bits to make up the 11-bit stack pointer are the 3 lsbs of the sph byte located at b7h.
rev. 0 e16e aduc831 data pointer (dptr) the data pointer is made up of thre e 8-bit registers, named dpp (page byte), dph (high byte) and dpl (low byte). these are used to provide memory addresses for internal and external code access and external data access. it may be m anipulated as a 16-bit register (dptr = dph, dpl), although inc dptr instructions will automatically carry over to dpp, or as three independent 8-bit registers (dpp, dph, dpl). the aduc831 supports dual data pointers. refer to the dual data pointer section. program status word (psw) the psw sfr contains several bits reflecting the current status of the cpu as detailed in table i. sfr address d0h power-on default value 00h bit addressable yes table i. psw sfr bit designations bit name description 7c yc arry flag 6a ca uxiliary carry flag 5f 0g eneral-purpose flag 4 rs1 register bank select bits 3 rs0 rs1 rs0 selected bank 000 011 102 113 2o vo verflow flag 1f 1g eneral-purpose flag 0p parity bit power control sfr (pcon) the pcon sfr contains bits for power-saving options and general-purpose status flags as shown in table ii. sfr address 87h power-on default value 00h bit addressable no table ii. pcon sfr bit designations bit name description 7 smod double uart baud rate 6 seripd i 2 c/spi power-down interrupt enable 5 int0pd int0 pdie aeo daeo 1 p 0 p 1p d pde 0 id ie
rev. 0 aduc831 e17e spicon 1 f8h 04h dac0l f9h 00h dac0h fah 00h dac1l fbh 00h dac1h fch 00h daccon fdh 04h reserved b 1 f0h 00h adcofsl 3 f1h 00h adcofsh 3 f2h 20h adcg a inl 3 f3h 00h adcg a inh 3 f4h 00h adccon3 f5h 00h reserved i2ccon 1 e8h 00h reserved acc 1 e0h 00h reserved adccon2 1 d8h 00h adcd atal d9h 00h adcd atah dah 00h reserved psw 1 d0h 00h dmal d2h 00h dmah d3h 00h dmap d4h 00h reserved t2con 1 c8h 00h rcap2l cah 00h rcap2h cbh 00h tl2 cch 00h th2 cdh 00h reserved wdcon 1 c0h 10h ip 1 b8h 00h econ b9h 00h edata1 bch 00h edata2 bdh 00h ie 1 a8h 00h ieip2 a9h a0h p2 1 a0h ffh scon 1 98h 00h sbuf 99h 00h i2cdat 9ah 00h not used p1 1, 2 90h ffh not used tcon 1 88h 00h tmod 89h 00h tl0 8ah 00h tl1 8bh 00h th0 8ch 00h th1 8dh 00h p0 1 80h ffh sp 81h 07h dpl 82h 00h dph 83h 00h dpp 84h 00h reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used not used not used p3 1 b0h ffh not used not used not used not used not used spidat f7h 00h adccon1 efh 00h reserved psmcon dfh deh edarl c6h 00h edata3 beh 00h edata4 bfh 00h not used pcon 87h 00h ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 eeh 0 mco edh 0 ech 0 ebh 0 eah e9h 0 e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits adci dfh 0 dma deh 0 cconv ddh 0 sconv dch 0 cs3 dbh 0 cs2 dah cs1 d9h 0 cs0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rs1 d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre3 c7h 0 pre2 c6h 0 pre1 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 wdwr c0h 0 bits psi bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah ti 99h 0 ri 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 ie0 89h 0 it0 88h 0 tcon 88h 00h mnemonic sfr address default value mnemonic default value sfr address these bits are contained in this byte. sfr map key: notes: 1 sfrs whose address ends in 0h or 8h are bit addressable. 2 the primary function of port1 is as an analog input port; therefore, to enable the digital secondary functions on these port pins, write a '0' to the corresponding port 1 sfr bit. 3 calibration coefficients are preconfigured on power-up to factory calibrated values. 4 value depends on external crystal. 1 reserved reserved reserved 0 0 0 0 0 0 0 0 0 0 0 0 11 timecon hthsec sec min hour intval dpcon a1h a2h a3h a4h a5h a6h a7h 00h 00h 00h 00h 00h 00h 00h reserved reserved reserved reserved reserved reserved pwmcon aeh 00h cfg831 4 afh 10h reserved reserved t3fd t3con 9dh 9eh 00h 00h pwm0l pwm0h pwm1l pwm1h sph 00h 00h 00h 00h 00h b1h b2h b3h b4h b7h reserved reserved reserved chipid c2h 3xh edarh c7h 00h mde i2cm reserved pre0 mdi i2crs i2ctx i2ci i2cadd 9bh 55h figure 6. special function register locations and reset values special function registers all registers except the program counter and the four general- purpose register banks, reside in the special function register (sfr) area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and other on-chip peripherals. figure 6 shows a full sfr memory map and sfr contents on reset. unoccupied sfr locations are shown dark-shaded in the figure below (not used). unoccupied locations in the sfr address space are not implemented, i.e., no register exists at this location. if an unoccupied location is read, an unspecified value is returned. sfr locations reserved for on-chip testing are shown lighter shaded below (reserved) and should not be accessed by user software. sixteen of the sfr locations are also bit addressable and denoted by '1' in the figure below, i.e., the bit addressable sfrs are those whose address ends in 0h or 8h.
rev. 0 e18e aduc831 adc circuit information general overview the adc conversion block incorporates a fast, 8-channel, 12-bit, single supply adc. this block provides the user with multichannel mux, track/hold, on-chip reference, calibration features, and adc. all components in this block are easily configured via a 3-register sfr interface. the adc consists of a conventional successive-approximation converter based around a capacitor dac. the converter accepts an analog input range of 0 to v ref . a high precision, low drift, and factory calibrated 2.5 v reference is provided on-chip. an external reference can be connected as described later. this external reference can be in the range of 1 v to av dd . single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an exter- nal pin. timer 2 can also be configured to generate a repetitive trigger for adc conversions. the adc may be configured to operate in a dma mode whereby the adc block continuously converts and captures samples to an external ram space without any interaction from the mcu core. this automatic capture facility can extend through a 16 mbyte external data memory space. the aduc831 is shipped with factory programmed calibration coefficients that are automatically downloaded to the adc on power-up ensuring optimum adc performance. the adc core contains internal offset and gain calibration registers, that can be hardware calibrated to minimize system errors. a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front end adc multiplexor (effectively a ninth adc channel input) facilitating a temperature sensor implementation. adc transfer function the analog input range for the adc is 0 v to v ref . for this r ange, the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs, . . ., fs e3/2 lsbs). the output coding is straight binary with 1 lsb = fs/4096 or 2.5 v/4096 = 0.61 mv when v ref = 2.5 v. the ideal input/output transfer characteristic for the 0 to v ref range is shown in figure 7. output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 0v 1lsb +fs e1lsb voltage input 1lsb = fs 4096 figure 7. adc transfer function typical operation once configured via the adccon 1-3 sfrs the adc will convert the analog input and provide an adc 12-bit result word in the adcdatah/l sfrs. the top four bits of the adcdatah sfr will be written with the channel selection bits so as to identify the channel result. the format of the adc 12 bit result word is shown in figure 8. cheid top 4 bits high 4 bits of adc result word low 8 bits of the adc result word adcdatah sfr adcdatal sfr figure 8. adc result format
rev. 0 aduc831 e19e table iii. adccon1 sfr bit designations bit name description adccon1.7 md1 the mode bit selects the active operating mode of the adc. set by the user to power up the adc. cleared by the user to power down the adc. adccon1.6 ext_ref set by the user to select an external reference. cleared by the user to use the internal reference. adccon1.5 ck1 the adc clock divide bits (ck1, ck0) select the divide ratio for the master clock used to generate the adccon1.4 ck0 adc clock. to ensure correct adc operation, the divider ratio must be chosen to reduce the adc clock to 4.5 mhz and below. a typical adc conversion will require 17 adc clocks. the divider ratio is selected as follows: ck1 ck0 mclk divider 0016 012 104 118 adccon1.3 aq1 the adc acquisition select bits (aq1, aq0) select the time provided for the input track-and-hold amplifier adccon1.2 aq0 to acquire the input signal. an acquisition of three or more adc clocks is recommended; clocks are selected as follows: aq1 aq0 #adc clks 001 012 103 114 adccon1.1 t2c the timer 2 conversion bit (t2c) is set by the user to enable the timer 2 overflow bit be used as the adc convert start trigger input. adccon1.0 exc the external trigger enable bit (exc) is set by the user to allow the external pin p3.5 (convst) to be used as the active low convert start input. this input should be an active low pulse (minimum pulsewidth >100 ns) at the required sample rate. adccon1 e (adc control sfr #1) the adccon1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. sfr address: efh sfr power-on default value: 00h bit addressable: no
rev. 0 e20e aduc831 table iv. adccon2 sfr bit designations bit name description adccon2.7 adci the adc interrupt bit (adci) is set by hardware at the end of a single adc conversion cycle or at the end of a dma block conversion. adci is cleared by hardware when the pc vectors to the adc inter- rupt service routine. otherwise, the adci bit should be cleared by user code. adccon2.6 dma the dma mode enable bit (dma) is set by the user to enable a preconfigured adc dma mode opera- tion. a more detailed description of this mode is given in the adc dma mode section. the dma bit is automatically set to 0 at the end of a dma cycle. setting this bit causes the ale output to cease, it will start again when dma is started and will operate correctly after dma is complete. adccon2.5 cconv the continuous conversion bit (cconv) is set by the user to initiate the adc into a continuous mode of conversion. in this mode, the adc starts converting based on the timing and channel configuration al r eady set up in the a dccon sfrs; the adc automatically starts another conversion once a previ- ous conversion has completed. adccon2.4 sconv the single conversion bit (sconv) is set to initiate a single conversion cycle. the sconv bit is automatically reset to 0 on com pletion of the single conversion cycle. adccon2.3 cs3 the channel selection bits (cs3-0) allow the user to program the adc channel selection under adccon2.2 cs2 software control. when a conversion is initiated, the channel converted will be the one pointed to by adccon2.1 cs1 these channel selection bits. in dma mode, the channel selection is derived from the channel id adccon2.0 cs0 written to the external memory. cs3 cs2 cs1 cs0 ch# 00000 00011 00102 00113 01004 01015 01106 01117 1000t emp monitor requires minimum of 1
rev. 0 aduc831 e21e table v. adccon3 sfr bit designations bit name description adccon3.7 busy the adc busy status bit (busy) is a read-only status bit that is set during a valid adc conversion or calibration cycle. busy is auto matically cleared by the core at the end of conversion or calibration. adccon3.6 gncld gain calibration disable bit set to 0 to enable gain calibration. set to 1 to disable gain calibration. adccon3.5 avgs1 number of averages selection bits adccon3.4 avgs0 this bit selects the number of adc readings averaged during a calibration cycle. avgs1 avgs0 number of averages 0 0 15 0 1 1 1 0 31 1 1 63 adccon3.3 rsvd reserved. this bit should always be written as 0. adccon3.2 rsvd this bit should always be written as 1 by the user when performing calibration. adccon3.1 typical calibration type select bit. this bit selects between offset (zero-scale) and gain (full-scale) calibration. set to 0 for offset calibration. set to 1 for gain calibration. adccon3.0 scal start calibration cycle bit. when set, this bit starts the selected calibration cycle. it is automatically cleared when the calibration cycle is completed. adccon3 e (adc control sfr #3) the adccon3 register controls the operation of various calibra- tion modes as well as giving an indication of adc busy status. sfr address: f5h sfr power-on default value: 00h bit addressable: no
rev. 0 e22e aduc831 driving the a/d converter the adc incorporates a successive approximation (sar) archi- tecture involving a charge-sampled input stage. figure 9 shows the equivalent circuit of the analog input section. each adc conversion is divided into two distinct phases as defined by the position of the switches in figure 9. during the sampling phase (with sw1 and sw2 in the track position) a charge propor- tional to the voltage on the analog input is developed across the input sampling capacitor. during the conversion phase (with both switches in the hold position) the capacitor dac is adjusted via internal sar logic until the voltage on node a is zero, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor dac. the digital value finally contained in the sar is then latched out as the result of the adc conversion. control of the sar, and timing of acquisition and sampling modes, is handled a uto- matically by built-in adc control logic. acquisition and conversion times are also fully configurable under user control. capacitor dac comparator v ref agnd dac1 dac0 temperature monitor ain7 ain0 32pf agnd aduc831 node a sw1 sw2 track track hold hold 200 200 figure 9. internal adc structure note that whenever a new input channel is selected, a residual charge from the 32 pf sampling capacitor places a transient on the newly selected input. the signal source must be capable of recovering from this transient before the sampling switches click into hold mode. delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. one hardware solution would be to choose a very fast settling op amp to drive each analog input. such an op amp would need to fully settle from a small s ignal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. a better solution, recom- mended for use with any amplifier, is shown in figure 10. though at first glance the circuit in figure 10 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the nyquist frequency, even at a 200 khz sample rate. though the r/c does helps to reject some incoming high-frequency noise, its primary function is to ensure that the transient demands of the adc input stage are met. it ain0 aduc831 10 0.1 f figure 10. buffering analog inputs d oes so by providing a capacitive bank from which the 32 pf sampling capacitor can draw its charge. its voltage will not change by more than one count (1/4096) of the 12-bit trans- fer function when the 32 pf charge from a previous channel is dumped onto it. a larger capacitor can be used if desired, but not a larger resistor (for reasons described below). the schottky diodes in figure 10 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. they are not necessary if the op amp is powered from the same supply as the aduc831 since in that case the op amp is unable to generate voltages above v dd or below ground. an op amp of some kind is necessary unless the signal source is very low impedance to begin with. dc leakage currents at the aduc831?s analog inputs can cause measurable dc errors with external source impedances as little as 100 or so. to ensure accurate adc operation, keep the total source impedance at each analog input less than 61 . the table below illustrates examples of how source impedance can affect dc accuracy. source error from 1 ae rror from 10 a impedance leakage current leakage current 61 61 v = 0.1 lsb 610 v = 1 lsb 610 610 v = 1 lsb 6.1 mv = 10 lsb although figure 10 shows the op amp operating at a gain of 1, you can, of course, configure it for any gain needed. also, you can just as easily use an instrumentation amplifier in its place to condition differential signals. use any modern amplifier that is capable of delivering the signal (0 to v ref ) with minimal satura- tion. some single-supply rail-to-rail op amps that are useful for this purpose include, but are certainly not limited to, the ones given in table vi. check analog devices literature (cd rom data book, and so on) for details on these and other op amps and instrumentation amps. table vi. some single-supply op amps op amp model characteristics op281/op481 micropower op191/op291/op491 i/o good up to v dd , low cost op196/op296/op496 i/o to v dd , micropower, low cost op183/op283 high gain-bandwidth product op162/op262/op462 high gbp, micro package ad820/ad822/ad824 fet input, low cost ad823 fet input, high gbp
rev. 0 aduc831 e23e keep in mind that the adc?s transfer function is 0 to v ref , and a ny signal range lost to amplifier saturation near ground will impact dynamic range. though the op amps in table vi are cap able of delivering output signals very closely approaching g round, no amplifier can deliver signals all the way to ground when powered by a single supply. therefore, if a negative supply is available, you might consider using it to power the front end amplifiers. if you do, however, be sure to include the schottky diodes shown in figure 10 (or at least the lower of the two diodes) to protect the analog input from undervoltage condi- tions. to summarize this section, use the circuit of figure 10 to drive the analog input pins of the aduc831. voltage reference connections the on-chip 2.5 v band gap voltage reference can be used as the reference source for the adc and dacs. to ensure the accu- racy of the voltage reference, you must decouple the v ref pin to ground with a 0.1 f capacitor and the c ref pin to ground with a 0.1 f capacitor as shown in figure 11. buffer buffer 0.1 f 0.1 f 51 v ref c ref 2.5v band gap reference aduc831 figure 11. decoupling v ref and c ref if the internal voltage reference is to be used as a reference for external circuitry, the c ref output should be used. however, a buffer must be used in this case to ensure that no current is drawn from the c ref pin itself. the voltage on the c ref pin is that of an internal node within the buffer block, and its voltage is critical to adc and dac accuracy. on the aduc812 v ref was the recommended output for the external reference; this can be used but it should be noted that there will be a gain error between this reference and that of the adc. the aduc831 powers up with its internal voltage reference in the on state. this is available at the v ref pin, but as noted before there will be a gain error between this and that of the adc. the c ref output becomes available when the adc is powered up. if an external voltage reference is preferred, it should be connected to the v ref and c ref pins as shown in figure 12. bit 6 of the adccon1 sfr must be set to 1 to switch in the external reference voltage. to ensure accurate adc operation, the voltage applied to v ref must be between 1 v and av dd . in situations where analog input signals are proportional to the power supply (such as some strain gage applications) it may be desirable to connect the c ref and v ref pins directly to av dd . operation of the adc or dacs with a reference voltage below 1 v, however, may incur loss of accuracy eventually resulting in missing codes or non-monotonicity. for that reason, do not use a reference voltage less than 1 v. buffer 0.1 f 51 v ref c ref "1" = "0" = internal external 0.1 f 2.5v band gap reference aduc831 adccon1.6 v dd external voltage reference figure 12. using an external voltage reference to maintain compatibility with the aduc812, the external reference can also be connected to the v ref pin as shown in figure 13, to overdrive the internal reference. note this intro- duces a gain error for the adc that has to be calibrated out, thus the previous method is the recommended one for most users. for this method to work, adccon1.6 should be config- ured to use the internal reference. the external reference will then overdrive this. buffer 0.1 f 0.1 f 51 v ref c ref 2.5v band gap reference aduc831 external voltage reference v dd figure 13. using an external voltage reference
rev. 0 e24e aduc831 configuring the adc the aduc831?s successive approximation adc is driven by a divided down version of the master clock. to ensure adequate adc operation, this adc clock must be between 400 khz and 6 mhz, and optimum performance is obtained with adc clock between 400 khz and 4.5 mhz. frequencies within this range can easily be achieved with master clock frequencies from 400 khz to well above 16 mhz with the four adc clock divide ratios to choose from. for example, with a 12 mhz master clock, set the adc clock divide ratio to 4 (i.e., adcclk = mclk/4 = 3 mhz) by setting the appropriate bits in adccon1 (adccon1.5 = 1, adccon1.4 = 0). the total adc conversion time is 15 adc clocks, plus 1 adc clock for synchronization, plus the selected acquisition time (1, 2, 3, or 4 adc clocks). for the example above, with three clocks acquisition time, total conversion time is 19 adc clocks (or 6.3 s for a 3 mhz adc clock). in continuous conversion mode, a new conversion begins each time the previous one finishes. the sample rate is then simply the inverse of the total conversion time described above. in the example above, the continuous conversion mode sample rate would be 157.8 khz. if using the temperature sensor as the adc input, the adc should be configured to use an adcclk of mclk/16 and four acquisition clocks. increasing the conversion time on the temperature monitor channel improves the accuracy of the reading. to further improve the accuracy, an external reference with low tempera- ture drift should also be used. adc dma mode the on-chip adc has been designed to run at a maximum conversion speed of 4 s (247 khz sampling rate). when con- verting at this rate, the aduc831 microconverter has 4 s to read the adc result and store the result in memory for further postprocessing, otherwise the next adc sample could be lost. in an interrupt driven routine the microconverter would also have to jump to the adc interrupt service routine, which will also increase the time required to store the adc results. in applications where the aduc831 cannot sustain the interrupt rate, an adc dma mode is provided. to enable dma mode, bit 6 in adccon2 (dma) must be set. this allows the adc results to be written directly to a 16 mbyte external static memory sram (mapped into data memory space) without any interaction from the aduc831 core. this mode allows the aduc831 to capture a contiguous sample stream at full adc update rates (247 khz). a typical dma mode configuration example to set the aduc831 into dma mode a number of steps must be followed: 1. the adc must be powered down. this is done by ensuring md1 and md0 are both set to 0 in adccon1. 2. the dma address pointer must be set to the start address of where the adc results are to be written. this is done by writing to the dma mode address pointers dmal, dmah, and dmap. dmal must be written to first, followed by dmah, and then by dmap. 3. the external memory must be preconfigured. this consists of writing the required adc channel ids into the top four bits of every second memory location in the external sram starting at the first address specified by the dma address pointer. as the adc dma mode operates independent from the aduc831 core, it is necessary to provide it with a stop command. this is done by duplicating the last channel id to be converted followed by 1111 into the next channel selec- tion field. a typical preconfiguration of external memory is as follows. 11 1 1 00 1 1 00 1 1 100 0 010 1 00 1 0 00000ah 000000h stop command repeat last channel for a valid stop condition convert adc ch#3 convert temp sensor convert adc ch#5 convert adc ch#2 figure 14. typical dma external memory preconfiguration 4. the dma is initiated by writing to the adc sfrs in the following sequence: a. adccon2 is written to enable the dma mode, i.e., mov adccon2, #40h; dma mode enabled. b. adccon1 is written to configure the conversion time and power-up of the adc. it can also enable timer 2 driven conversions or external triggered conversions if required. c. adc conversions are initiated. this is done by starting single con versions, starting timer 2 running for timer 2 conversions or by receiving an external trigger. when the dma conversions are completed, the adc interrupt bit adci, is set by hardware and the external sram contains the new adc conversion results as shown below. it should be noted that no result is written to the last two memory locations. when the dma mode logic is active, it takes the responsibility of storing the adc results away from both the user and aduc831 core logic. as it writes the results of the adc conversions to external memory, it takes over the external memory interface from the core. thus, any core instructions that access the external memory while dma mode is enabled will not get access to it. the core will execute the instructions and they will take the same time to execute but they will not gain access to the external memory. no conversion result written here conversion result for adc ch#3 conversion result for temp sensor conversion result for adc ch#5 conversion result for adc ch#2 1111 0011 0011 100 0 010 1 0010 00000ah 000000h stop command figure 15. typical external memory configuration post adc dma operation
rev. 0 aduc831 e25e the dma logic operates from the adc clock and uses pipelining to perform the adc conversions and access the external memory at the same time. the time it takes to perform one adc conversion is called a dma cycle. the actions per- formed by the logic during a typical dma cycle are shown in the following diagram. write adc result converted during previous dma cycle read channel id to be converted during next dma cycle convert channel read during previous dma cycle dma cycle figure 16. dma cycle from the previous diagram, it can be seen that during one dma c ycle the following actions are performed by the dma logic: 1. an adc conversion is performed on the channel whose id was read during the previous cycle. 2. the 12-bit result and the channel id of the conversion per- formed in the previous cycle is written to the external memory. 3. the id of the next channel to be converted is read from external memory. for the previous example, the complete flow of events is shown in figure 16. because the dma logic uses pipelining, it takes three cycles before the first correct result is written out. m icro operation during adc dma mode during adc dma mode the microconverter core is free to continue code execution, including general housekeeping and communication tasks. however, note that mcu core accesses to ports 0 and 2 (which of course are being used by the dma controller) are gated off during adc dma mode of operation. this means that even though the instruction that accesses the external ports 0 or 2 will appear to execute, no data will be seen at these external ports as a result. note that during dma the internally contained xram ports 0 and 2 are available for use. the only case in which the mcu will be able to access xram during dma, is when the internal xram is enabled and the section of ram to which the dma adc results are being writ- ten to lies in an external xram. then the mcu will be able to access the internal xram only. this is also the case for use of the extended stack pointer. the microconverter core can be configured with an interrupt to be triggered by the dma controller when it had finished filling the requested block of ram with adc results, allowing the service routine for this interrupt to postprocess data without any real-time timing constraints. adc offset and gain calibration coefficients the aduc831 has two adc calibration coefficients, one for offset calibration and one for gain calibration. both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the special function register (sfr) area. the offset calibration coefficient is divided into adcofsh (six bits) and adcofsl (eight bits) and the gain calibration coefficient is divided into adcgainh (six bits) and adcgainl (eight bits). the offset calibration coefficient compensates for dc offset errors in both the adc and the input signal. increasing the offset coeffi- cient com pensates for positive offset, and effectively pushes the adc transfer function down. decreasing the offset coefficient compensates for negative offset, and effectively pushes the adc transfer function up. the maximum offset that can be compensated is typically 5% of v ref , which equates to typically 125 mv with a 2.5 v reference. similarly, the gain calibration coefficient compensates for dc gain errors in both the adc and the input signal. increasing the gain coefficient compensates for a smaller analog input signal range and scales the adc transfer function up, effectively increasing the slope of the transfer function. decreasing the gain coefficient, compensates for a larger analog input signal range and scales the adc transfer function down, effectively decreasing the slope of the transfer function. the maximum analog input signal range for which the gain coefficient can compensate is 1.025
rev. 0 e26e aduc831 initiating calibration in code when calibrating the adc, using adccon1 the adc should be set up into the configuration in which it will be used. the adccon3 register can then be used to set the device up and calibrate the adc offset and gain. mov adccon1,#08ch ;adc on; adcclk set ;to divide by 16, 4 ;acquisition clock to calibrate device offset: mov adccon2,#0bh ;select internal agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit, ;offset calibration to calibrate device gain: mov adccon2,#0ch ;select internal vref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration to calibrate system offset: connect system agnd to an adc channel input (0). mov adccon2,#00h ;select external agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit to calibrate system gain: connect system v ref to an adc channel input (1). mov adccon2,#01h ;select external vref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration the calibration cycle time, t cal , is calculated by the following equation assuming a 16 mhz crystal: t adcclk numav t cal acq = + 14 16 () for an adcclk/f core divide ratio of 16, a t acq = 4 adcclk, numav = 15, the calibration cycle time is: t t ms cal cal = + = 14 1 1000000 15 16 4 42 (/ ) ( ) . in a calibration cycle the adc busy flag (bit 7), instead of framing an individual adc conversion as in normal mode, will go high at the start of calibration and only return to zero at the end of the calibration cycle. it can therefore be monitored in code to indicate when the calibration cycle is completed. the following code can be used to monitor the busy signal during a calibration cycle: wait: mov a, adccon3 ;move adccon3 to a jb acc.7, wait ;if bit 7 is set jump to wait else continue
rev. 0 aduc831 e27e nonvolatile flash/ee memory flash/ee memory overview the aduc831 incorporates flash/ee memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code, and data memory sp ace. flash/ee me m ory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. this technology is basically an outgrowth of eprom technology and was developed through the late 1980s. flash/ee memory takes the flexible in-circuit reprogrammable features of eeprom and combines them with the space efficient/density features of eprom (see figure 17). because flash/ee technology is based on a single transistor cell architecture, a flash memory array, like eprom, can be imple- mented to achieve the space efficiencies or memory densities required by a given design. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. thus, flash memory is often and more correctly referred to as flash/ee memory. flash/ee memory technology space efficient/ density in-circuit reprogrammable eprom technology eeprom technology figure 17. flash/ee memory development overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programma- bility, high density and low cost. incorporated in the aduc831, flash/ee memory technology allows the user to update program code space in-circuit, without the need to replace onetime programmable (otp) devices at remote operating nodes. flash/ee memory and the aduc831 the aduc831 provides two arrays of flash/ee memory for user applications. 62 kbytes of flash/ee program space are provided on-chip to facilitate code execution without any external dis- crete rom device requirements. the program memory can be programmed in-circuit using the serial download mode provided, using conventional third party memory programmers, or via a user defined protocol that can configure it as data if required. a 4 kbyte flash/ee data memory space is also provided on- chip. this may be used as a general-purpose nonvolatile scratchpad area. user access to this area is via a group of six sfrs. this space can be programmed at a byte level, although it must first be erased in 4-byte pages. aduc831 flash/ee memory reliability the flash/ee program and data memory arrays on the aduc831 are fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four indepen- dent, sequential events. these events are defined as: a. initial page erase sequence b. read/verify sequence a single flash/ee c. byte program sequence memory d. second read/verify sequence endurance cycle in reliability qualification, every byte in both the program and data flash/ee memory is cycled from 00h to ffh until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the aduc831 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of e40 c to +25 c and +85 c to +125 c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the aduc831 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is reprogrammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, will derate with t j as shown in figure 18. 40 60 70 90 t j junction temperature e c retention e years 250 200 150 100 50 0 50 80 110 300 100 adi specification 100 years min. at t j = 55 c figure 18. flash/ee memory data retention
rev. 0 ?8 aduc831 using the flash/ee program memory the 62 kbyte flash/ee program memory array is mapped into the lower 62 kbytes of the 64 kbytes program space addressable by the aduc831, and is used to hold user code in typical applications. the program memory flash/ee memory arrays can be programmed in three ways: (1) serial downloading (in-circuit programming) the aduc831 facilitates code download via the standard uart serial port. the aduc831 will enter serial download mode after a reset or power cycle if the psen pin is pulled low through an external 1 k resistor. once in serial download mode, the user can download code to the full 62 kbytes of flash/ee program memory while the device is in circuit in its target application hardware. a pc serial download executable is provided as part of the aduc831 quickstart development system. the serial download protocol is detailed in a microconverter applications note uc004. (2) parallel programming the parallel programming mode is fully compatible with con- ventional third party flash or eeprom device programmers. in this mode ports p0, p1, and p2 operate as the external data and address bus interface, ale operates as the write enable strobe, and port p3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming. the high voltage (12 v) supply required for flash programming is generated using on-chip charge pumps to supply the high voltage program lines. the complete parallel programming specification is available on the microconverter home page at www.analog.com/microconverter. (3) user download mode (uload) in figure 19 we can see that it was possible to use the 62 kbytes of flash/ee program memory available to the user as one single block of memory. in this mode all of the flash/ee memory is read-only to user code. however, the flash/ee program memory can also be written to during runtime simply by entering uload mode. in uload mode the lower 56 kbytes of program memory can be erased and reprogrammed by user software as shown in figure 19. uload mode can be used to upgrade your code in the field via any user defined download protocol. configuring the spi port on the aduc831 as a slave, it is possible to completely repro- gram the 56 kbytes of flash/ee program memory in only 5 seconds (see uc007). alternatively, uload mode can be used to save data to the 56 kbytes of flash/ee memory. this can be extremely useful in data logging applications where the aduc831 can provide up to 60 kbytes of nv data memory on chip (4 kbytes of dedicated flash/ee data memory also exist). the upper 6 kbytes of the 62 kbytes of flash/ee program memory is only programmable via serial download or parallel programming. this means that this space appears as read only to user code. therefore, it cannot be accidentally erased or reprogrammed by erroneous code execution. this makes it very suitable to use the 6 kbytes as a bootloader. a bootload enable option exists in the serial downloader to ?lways run from e000h after reset.?if using a bootloader, this option is recommended to ensure that the bootloader always executes the correct code after reset. programming the flash/ee program memory via uload mode is described in more detail in the description of econ and also in technical note uc007. ffffh e000h dfffh 0000h user bootloader space the user bootloader space can be programmed in download/debug mode via the kernel but is read only when executing user code 6 kbyte f800h f7ffh user download space either the download/debug kernel or user code (in uload mode) can program this space. embedded download/debug kernel permanently embedded firmware allows code to be downloaded to any of the 62 kbytes of on-chip program memory. the kernel program appears as 'nop' instruc- tions to user code. 56 kbyte 2 kbyte 62 kbytes of user code memory figure 19. flash/ee program memory map in uload mode flash/ee program memory security the aduc831 facilitates three modes of flash/ee program memory security. these modes can be independently acti- vated, restricting access to the internal code space. these security modes can be enabled as part of serial download protocol as described in technical note uc004 or via parallel programming. the security modes available on the aduc831 are described as follows: lock mode this mode locks the code memory, disabling parallel program- ming of the program memory. however, reading the memory in parallel mode and reading the memory via a movc command from external memory is still allowed. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. secure mode this mode locks code in memory, disabling parallel programming (program and verify/read commands) as well as disabling the execution of a ?ovc?instruction from external memory, which is attempting to read the op codes from internal memory. read/ write of internal data flash/ee from external memory is also disabled. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. serial safe mode this mode disables serial download capability on the device. if serial safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., reset asserted and de-asserted with psen low, the part will interpret the serial download reset as a normal reset only. it will therefore not enter serial download mode but only execute a normal reset sequence. serial safe mode can only be disabled by initiating a code-erase command in parallel programming mode.
rev. 0 aduc831 e29e using the flash/ee data memory the 4 kbytes of flash/ee data memory is configured as 1024 pages, each of four bytes. as with the other aduc831 peripherals, the interface to this memory space is via a group of registers mapped in the sfr space. a group of four data registers (edata1e4) are used to hold the four bytes of data at each page. the page is addressed via the two registers eadrh and eadrl. finally, econ is an 8-bit control register that may be written with one of nine flash/ee memory access commands to trigger various read, write, erase, and verify functions. a block diagram of the sfr interface to the flash/ee data memory array is shown in figure 20. econ?flash/ee memory control sfr programming of either the flash/ee data memory or the flash/ee program memory is done through the flash/ee memory control sfr (econ). this sfr allows the user to read, write, erase, or verify the 4 kbytes of flash/ee data memory or the 56 kbytes of flash/ee program memory. b yte 1 (0000h) edata1 sfr b yte 1 (0004h) b yte 1 (0008h) b yte 1 ( 000ch) b yte 1 (0 ff8h) b yte 1 (0 ffch) b yte 2 (0001h) edata2 sfr b yte 2 (0005h) b yte 2 (0009h) byte 2 ( 000dh) b yte 2 (0 ff9h) byte 2 (0 ffdh) b yte 3 (0002h) edata3 sfr b yte 3 (0006h) b yte 3 (000ah) b yte 3 (000eh) b yte 3 (0 ffah) b yte 3 (0 ffeh) b yte 4 (0003h) edata4 sfr b yte 4 (0007h) b yte 4 ( 000bh) byte 4 ( 000fh) byte 4 (0 ffbh) b yte 4 (0 fffh) 01h 00h 02h 03h 3feh 3ffh page address (e adrh/l) b yte a ddresses are given in brackets figure 20. fl ash/ee data memory control and configu ration table vii. econ?flash/ee memory commands command description command description econ value (normal mode) (power-on default) (uload mode) 01h results in 4 bytes in the flash/ee data memory, not implemented. use the movc instruction. read addressed by the page address eadrh/l, being read into edata1e4. 02h results in four bytes in edata 1e4 being written to results in bytes 0-255 of internal xram being written write the flash/ee data memory, at the page address given by to the 256 bytes of flash/ee program memory at the eadrh/l (0 eadrh/l < 0400h. page address given by eadrh. (0 eadrh < e0h) note: the four bytes in the page being addressed must n ote: the 256 bytes in the page being addressed must be pre-erased. be pre-erased. 03h reserved command reserved command 04h verifies if the data in edata1e4 is contained in the not implemented. use the movc and movx verify page address given by eadrh/l. a subsequent read instructions to verify the write in software. of the econ sfr will result in a 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. 05h results in the erase of the 4-byte page of flash/ee data r esults in the 64-byte page of flash/ee program erase page mem ory addressed by the page address eadrh/l. memory, addressed by the byte address eadrh/l being erased. eadrl can equal any of 64 locations within the page. a new page starts whenever eadrl is equal to 00h, 40h, 80h, or c0h. 06h results in the erase of entire 4 kbytes of flash/ee results in the erase of the entire 56 kbytes of uload erase all data memory. flash/ee program memory. 81h results in the byte in the flash/ee data memory, not implemented. use the movc command. readbyte addressed by the byte address eadrh/l, being read into edata1. (0 eadrh/l 0fffh). 82h results in the byte in edata1 being written into results in the byte in edata1 being written into wri t eb yte flash/ee data memory, at the byte address eadrh/l. flash/ee program memory, at the byte address eadrh/l (0 eadrh/l dfffh). 0fh leaves the econ instructions to operate on the enters normal mode directing subsequent econ exuload flash/ee data memory. instructions to operate on the flash/ee data memory. f0h enters uload mode, directing subsequent econ leaves the econ instructions to operate on the uload instructions to operate on the flash/ee program memory. flash/ee program memory.
rev. 0 e30e aduc831 example: programming the flash/ee data memory a user wishes to program f3h into the second byte on page 03h of the flash/ee data memory space while preserving the other three bytes already in this page. a typical program of the flash/ ee data array will involve: 1) setting eadrh/l with the page address 2) writing the data to be programmed to the edata1e4 3) writing the econ sfr with the appropriate command step 1: set up the page address the two address registers eadrh and eadrl hold the high byte address and the low byte address of the page to be addressed. the assembly language to set up the address may appear as: mov eadrh,#0 ; set page address pointer mov eadrl,#03h step 2: set up the edata registers we must now write the four values to be written into the page into the four sfrs edatae14. unfortunately, we do not know three of them. thus, we must read the current page and over- write the second byte. mov econ,#1 ; read page into edata1-4 mov edata2,#0f3h ; overwrite byte 2 step 3: program page a byte in the flash/ee array can only be programmed if it has previously been erased. to be more specific, a byte can only be programmed if it already holds the value ffh. because of the flash/ee architecture, this erase must happen at a page level; therefore, a minimum of four bytes (one page) will be erased when an erase command is initiated. once the page is erased we can program the four bytes in-page and then perform a verification of the data. mov econ,#5 ; erase page mov econ,#2 ; write page mov econ,#4 ; verify page mov a,econ ; check if econ=0 (ok!) jnz error although the 4 kbytes of flash/ee data memory are shipped from the factory pre-erased, i.e., byte locations set to ffh, it is nonethe less good programming practice to include an erase-all routine as part of any configuration/setup code running on the adu c 831. an erase-all command consists of writing 06h to th e econ sfr, which initiates an erase of the 4 kb yte flash/ee array. this command coded in 8051 assembly would appear as: mov econ,#06h ; erase all command ; 2 ms duration flash/ee memory timing typical program and erase times for the aduc831 are as follows: normal mode (operating on flash/ee data memory) readpage (4 bytes) e 5 machine cycles writepage (4 bytes) e 380 s verifypage (4 bytes) e 5 machine cycles erasepage (4 bytes) e 2 ms eraseall (4 kbytes) e 2 ms readbyte (1 byte) e 3 machine cycle writebyte (1 byte) e 200 s uload mode (operating on flash/ee program memory) writepage (256 bytes) e 15 ms erasepage (64 bytes) e 2 ms eraseall (56 kbytes) e 2 ms writebyte (1 byte) e 200 s it should be noted that a given mode of operation is initiated as soon as the command word is written to the econ sfr. the core microcontroller operation on the aduc831 is idled until the requested program/read or erase mode is completed. in practice, this means that even though the flash/ee memory mode of operation is typically initiated with a two-machine cycle mov instruction (to write to the econ sfr), the next instruc- tion will not be executed until the f lash/ee operation is complete. this means that the core will not respond to interrupt requests until the flash/ee opera tion is complet e, although the core peripheral functions like counter/timers will continue to count and time as configured throughout this period.
rev. 0 aduc831 e31e aduc831 configuration sfr (cfg831) the cfg831 sfr contains the necessary bits to configure the internal xram, eprom controller, pwm output selection and frequency, dac buffer, and the extended sp. by default it configures the user into 8051 mode, i.e., extended sp is disabled, internal xram is disabled. cfg831 aduc831 config sfr sfr address afh power-on default value 10 * h bit addressable no table viii. cfg831 sfr bit designations bit name description 7 exsp extended sp enable. when set to 1 by the user, the stack will rollover from sph/sp = 00ffh to 0100h. when set to 0 by the user, the stack will roll over from sp = ffh to sp = 00h. 6 pwpo pwm pin out selection. set to 1 by the user = pwm output pins selected as p3.4 and p3.3. set to 0 by the user = pwm output pins selected as p2.6 and p2.7. 5 dbuf dac output buffer. set to 1 by the user = dac . output buffer bypassed. set to 0 by the user = dac output buffer enabled. 4 epm2 flash/ee controller and pwm clock frequency configuration bits. 3 epm1 frequency should be configured such that fosc/divide factor = 32 khz + 50%. 2 epm0 epm2 epm1 epm0 divide factor 000 32 001 64 010 128 011 256 100 512 10 1 1024 1 rsvd reserved. this bit should always contain 0. 0 xramen xram enable bit. when set to 1 the internal xram will be mapped into the lower 2 kbytes of the external address space. when set to 0 the internal xram will not be accessible and the external data memory will be mapped into the lower 2 kbytes of external data memory. * note that the flash/ee controller bits epm2, epm1, epm0 are set to their correct values depending on the crystal frequency at power-up. the user should not modify these bits so all instructions to the cfg831 register should use the orl, xrl, or anl instructions. value of 10h is for a 11.0592 mhz crystal.
rev. 0 e32e aduc831 user interface to other on-chip aduc831 peripherals the following section gives a brief overview of the various peripherals also available on-chip. a summary of the sfrs used to control and configure these peripherals is also given. dac the aduc831 incorporates two 12-bit, voltage output dacs on-chip. each has a rail-to-rail voltage output buffer capable of driving 10 k /100 pf. each has two selectable ranges, 0 v to v ref (the internal band gap 2.5 v reference) and 0 v to av dd . each can operate in 12-bit or 8-bit mode. both dacs share a control register, daccon, and four data registers, dac1h/l, dac0h/l. it should be noted that in 12-bit asynchronous mode, the dac voltage output will be updated as soon as the dacl data sfr has been written; therefore, the dac data registers should be updated as dach first, followed by dacl. note: for correct dac operation on the 0 to v ref range, the adc must be switched on. this results in the dac using the correct reference value. daccon dac control register sfr address fdh power-on default value 04h bit addressable no table ix. daccon sfr bit designations bit name description 7 mode the dac mode bit sets the overriding operating mode for both dacs. set to 1 = 8-bit mode (write 8 bits to dacxl sfr). set to 0= 12-bit mode. 6 rng1 dac1 range select bit. set to 1 = dac1 range 0ev dd . set to 0 = dac1 range 0ev ref . 5 rng0 dac0 range select bit. set to 1 = dac0 range 0ev dd. set to 0 = dac0 range 0ev ref. 4 clr1 dac1 clear bit. set to 0 = dac1 output forced to 0 v. set to 1 = dac1 output normal. 3 clr0 dac0 clear bit. set to 0 = dac1 output forced to 0 v. set to 1 = dac1 output normal. 2 sync dac0/1 update synchronization bit. when set to 1 the dac outputs update as soon as dacxl sfrs are written. the user can simultaneously update both dacs by first updating the dacxl/h sfrs while sync is 0. both dacs will then update simultaneously when the sync bit is set to 1. 1 pd1 dac1pd s1podac1 s0podac1 0 pd0 dac0pd s1podac0 s0podac0 dac dacdr dacdrdac sra dac0dac0d) dac1dac1d) dac0dac0d) adac1dac1d) c podv 00 ar a n ar t1dacdacdac dac
rev. 0 aduc831 e33e using the dac the on-chip dac architecture consists of a resistor string dac followed by an output buffer amplifier, the functional equivalent of which is illustrated in figure 21. details of the actual dac architecture can be found in u.s. patent number 5969657 (www.uspto.gov). features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. output buffer high z disable (from mcu) dac0 r r r r r aduc831 av dd v ref figure 21. resistor string dac functional equivalent as illustrated in figure 21, the reference source for each dac is user selectable in software. it can be either av dd or v ref. in 0-to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin. in 0-to-v ref mode, the dac output transfer function spans from 0 v to the internal v ref, or if an external reference is applied, the voltage at the v ref pin. the dac output buffer amplifier features a true rail- to-rail output stage implementation. this means that, unloaded, each output is capable of swinging to within less than 100 mv of both av dd and ground. moreover, the dac?s linearity specifi- cation (when driving a 10 k resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in 0-to-av dd mode only, codes 3945 to 4095. linear- ity degradation near ground and v dd is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 22. the dotted line in figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. note that figure 22 represents a transfer function in 0-to-v dd mode only. in 0-to-v ref mode (with v ref < v dd ) the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the ideal line right to the end (v ref in this case, not v dd ), showing no signs of endpoint linearity errors. v dd v dd e50mv v dd e100mv 100mv 50mv 0mv 000h fffh figure 22. endpoint nonlinearities due to amplifier saturation the end point nonlinearities conceptually illustrated in figure 22 get worse as a function of output loading. most of the aduc831?s data sheet specifications assume a 10 k resistive load to ground at the dac output. as the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of figure 22 become larger. with larger current demands, this can significantly limit output voltage swing. figure 23 and figure 24 illustrate this behavior. it should be noted that the upper trace in each of these figures is only valid for an output range selection of 0-to-av dd . in 0-to- v ref mode, dac loading will not cause highside voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. for example, if av dd = 3 v and v ref = 2.5 v, the highside voltage will not be affected by loads less than 5 ma. but somewhere around 7 ma the upper curve in figure 24 drops below 2.5 v (v ref ) indicating that at these higher currents the output will not be capable of reaching v ref . source/sink current e ma 5 0510 15 output voltage e v 4 3 2 1 0 dac loaded with 0000h dac loaded with 0fffh figure 23. source and sink current capability with v ref = v dd = 5 v
rev. 0 e34e aduc831 source/sink current e ma 3 0510 15 output voltage e v 2 1 0 dac loaded with 0000h dac loaded with 0fffh figure 24. source and sink current capability with v ref = v dd = 3 v to reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors, the internal buffer can be bypassed. this is done by setting the dbuf bit in the cfg831 register. this allows a full rail-to-rail output from the dac which should then be buffered externally using a dual supply op-amp in order to get a rail-to-rail output. this external buffer should be located as near as physically possible to the dac output pin on the pcb. note the unbuffed mode only works in the 0 to v ref range. to drive significant loads with the dac outputs, external buff- ering may be required (even with the internal buffer enabled), as illustrated in figure 25. a list of recommended op-amps is in table vi. aduc831 dac0 dac1 figure 25. buffering the dac outputs the dac output buffer also features a high-impedance disable function. in the chip?s default power-on state, both dacs are disabled, and their outputs are in a high-impedance state (or three-state) where they remain inactive until enabled in software. this means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each dac output. assuming this resistor is in place, the dac outputs will remain at ground potential whenever the dac is disabled.
rev. 0 aduc831 e35e table x. pwmcon sfr bit designations bit name description 7 sngl turns off pwm output at p2.6 or p3.4 leaving port pin free for digital i/o. 6 md2 pwm mode bits 5 md1 the md2/1/0 bits choose the pwm mode as follows: 4 md0 md2 md1 md0 mode 000m ode 0: pwm disabled 001m ode 1: single variable resolution pwm on p2.7 or p3.3 010m ode 2: twin 8-bit pwm 011m ode 3: twin 16-bit pwm 100m ode 4: dual nrz 16-bit - dac 101m ode 5: dual 8-bit pwm 110m ode 6: dual rz 16-bit - dac 111r eserved for future use 3c div1 pwm clock divider 2c div0 scale the clock source for the pwm counter as shown below: cdiv1 cdiv0 description 00 pwm counter = selected clock/1 01 pwm counter = selected clock/4 10 pwm counter = selected clock/16 11 pwm counter = selected clock/64 1 csel1 pwm clock divider 0 csel0 select the clock source for the pwm as shown below: csel1 csel0 description 00 pwm clock = f ocs/divide factor /15 (see cfg831 register) 01 pwm clock = f ocs/divide factor (see cfg831 register) 10 pwm clock = external input at p3.4/t0 11 pwm clock = f osc pulsewidth modulator (pwm) the pwm on the aduc831 is highly flexible pwm offering programmable resolution and input clock, and can be config- ured for any one of six different modes of operation. two of these modes allow the pwm to be configured as a
rev. 0 e36e aduc831 pwm modes of operation mode 0: pwm disabled the pwm is disabled, allowing p2.6 and p2.7 to be used as normal. mode 1: single variable resolution pwm in mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the pwm to be variable. pwm1h/l sets the period of the output waveform. reducing pwm1h/l reduces the resolution of the pwm output but increases the maximum output rate of the pwm. (for example, setting pwm1h/l to 65536 gives a 16-bit pwm with a maximum output rate of 244 hz (16 mhz/65536). setting pwm1h/l to 4096 gives a 12-bit pwm with a maximum output rate of 3906 hz (16 mhz/4096).) pwm0h/l sets the duty cycle of the pwm output waveform, as shown in the diagram below. p2.7 pwm counter pwm1h/l 0 pwm0h/l figure 27. aduc831 pwm in mode 1 mode 2: twin 8-bit pwm in mode 2, the duty cycle of the pwm outputs and the resolution of the pwm outputs are both programmable. the maximum resolution of the pwm output is eight bits. pwm1l sets the period for both pwm outputs. typically, this will be set to 255 (ffh) to give an 8-bit pwm, although it is possible to reduce this as necessary. a value of 100 could be loaded here to give a percentage pwm (i.e., the pwm is accurate to 1%). the outputs of the pwm at p2.6 and p2.7 are shown in the diagram below. as can be seen, the output of pwm0 (p2.6) goes low when the pwm counter equals pwm0l. the output of pwm1 (p2.7) goes high when the pwm counter equals pwm1h, and goes low again when the pwm counter equals pwm0h. setting pwm1h to 0 ensures that both pwm outputs start simultaneously. p2.7 p2.6 pwm counter pwm1h 0 pwm1l pwm0h pwm0l figure 28. pwm mode 2 mode 3: twin 16-bit pwm in mode 3, the pwm counter is fixed to count from 0 to 65536 giving a fixed 16-bit pwm. operating from the 16 mhz core clock results in a pwm output rate of 244 hz. the duty cycle of the pwm outputs at p2.6 and p2.7 are independently programmable. as shown in figure 29, while the pwm counter is less than pwm0h/l, the output of pwm0 (p2.6) is high. once the pwm counter equals pwm0h/l, then pwm0 (p2.6) goes low and remains low until the pwm counter rolls over. similarly while the pwm counter is less than pwm1h/l, the output of pwm1 (p2.7) is high. once the pwm counter equals pwm1h/l, then pwm1 (p2.7) goes low and remains low until the pwm counter rolls over. in this mode, both pwm outputs are synchronized. once the pwm counter rolls over to 0, both pwm0 (p2.6) and pwm1 (p2.7) will go high. p2.7 p2.6 pwm counter pwm1h/l 0 65536 pwm0h/l figure 29. pwm mode 3
rev. 0 aduc831 e37e mode 4: dual nrz 16-bit - dac mode 4 provides a high speed pwm output similar to that of a
rev. 0 e38e aduc831 serial peripheral interface the aduc831 integrates a complete hardware serial peripheral interface (spi) on-chip. spi is an industry standard syn chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. it should be noted that the spi pins are shared with the i 2 c interface pins. t herefore, the user can only enable one or the other interface at any given time (see spe in table xi b elow). the spi port can be configured for master or slave op eration, and typically consists of four pins, namely: miso (master in, slave out data i/o pin) the miso (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. mosi (master out, slave in pin) the mosi (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclock (serial clock i/o pin) the master serial clock (sclock) is used to synchronize the data being transmitted and received through the mosi and miso data lines. a single data bit is transmitted and received in each sclock period. therefore, a byte is transmitted/received after eight sclock periods. the sclock pin is configured as an output in master mode and as an input in slave mode. in master mode the bit-rate, polarity and phase of the clock are controlled by the cpol, cpha, spr0, and spr1 bits in the spicon sfr (see table xi). in slave mode the spicon register will have to be configured with the phase and polarity (cpha and cpol) of the ex pected input clock. in both master and slave modes, the data is transm itted on one edge of the sclock signal and sampled on the other. it is important therefore, that the cpha and cpol are configured the same for the master and slave devices. slave select input pin ( ss ) tss ss )adc i crp1 td ss adc1 spiicpa1 ss wcpa0 ss ispi ss spr0spiconsr tsrspi spicon spicr sra podv oo a ti spiconsrd n d ispi spii scspi cspidatsr wco wce scspidatspi c spe spiie sspi ci c spi spiss sscoc) csscoc) cpo cps sscoc cscoc cpa cps sscoc cscoc 1 spr1 spirs 0 spr0 tscoc) spr1 spr0 sr 00 osc 01 osc 10 osc 11 osc 1 i sp i s spi0 ss spr0 tcpocpa
rev. 0 aduc831 e39e spidat spi data register function the spidat sfr is written by the user to transmit data over the spi interface or read by user code to read data just received by the spi interface. sfr address f7h power-on default value 00h bit addressable no spi interface?master mode in master mode, the sclock pin is always an output and gener- ates a burst of eight clocks whenever user code writes to the spidat register. the s clock bit rate is determined by sp r0 and spr1 in spicon. it should also be noted that the ss iadc1 ss i spidate scocspidatosi wscociso a tispi t spidat spiis iscoct ss tspidati iso osiscoca tispi tspidat t cpa1 ss cpa0 spii dspiconsr tiadc1spi adc1spi a spiispi) scoc cp o1) scoc cp o0) cpa 1) cpa 0) sapeinpt ispia dataotpt ispia sapeinpt dataotpt s it it it it it it1 s s it it it it it it1 s ss spita
rev. 0 e40e aduc831 i 2 c compatible interface the aduc831 supports a fully licensed * i 2 c serial interface. the i 2 c interface is implemented as a full hardware slave and software master. sdata is the data i/o pin and sclock is the serial clock. these two pins are shared with the mosi and sclock pins of the on-chip spi interface. therefore, the user can only enable one or the other interface at any given time (see spe in spicon previously). application note uc001 describes the operation of this interface as implemented, and is available from the microconverter website at www.analog.com/microconverter. three sfrs are used to control the i 2 c interface. these are described below: i2ccon i 2 c control register sfr address e8h power-on default value 00h bit addressable yes table xii. i2ccon sfr bit designations bit name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sdata pin if the data output enable (mde) bit is set. 6 mde i 2 c software master data output enable bit (master mode only). set by user to enable the sdata pin as an output (tx). cleared by the user to enable sdata pin as an input (rx). 5 mco i 2 c software master clock output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written on this bit will be output on the sclock pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the sdata pin is latched into this bit on sclock if the data output enable (mde) bit is ?0.? 3 i2cm i 2 c master/slave mode bit. set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by user to reset the i 2 c interface. cleared by user code for normal i 2 c operation. 1i 2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting. cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared automatically when user code reads the i2cdat sfr (see i2cdat below). i2cadd i 2 c address register function holds the i 2 c peripheral address for the part. it may be overwritten by user code. technical note uc001 at www.analog.com/microconverter describes the format of the i 2 c standard 7-bit address in detail. sfr address 9bh power-on default value 55h bit addressable no i2cdat i 2 c data register function the i2cdat sfr is written by the user to transmit data over the i 2 c interface or read by user code to read d ata just received by the i 2 c int er face. accessing i2cdat automatically clears any pending i 2 c i nte r rupt and the i2ci bit in the i2c con sfr. user software should only access i2cdat once per interrupt cycle. sfr address 9ah power-on default value 00h bit addressable no * purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use the aduc831 in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
rev. 0 aduc831 e41e the main features of the microconverter i 2 c interface are: ? only two bus lines are required; a serial data line (sdata) and a serial clock line (sclock). ? an i 2 c master can communicate with multiple slave devices. because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment (figure 34). ? on-chip filtering rejects <50 ns spikes on the sdata and the sclock lines to preserve data integrity. dv dd i 2 c master i 2 c slave #1 i 2 c slave #2 figure 34. typical i 2 c system software master mode the aduc831 can be used as an i 2 c master device by configur- ing the i 2 c peripheral in master mode and writing software to output the data bit by bit. this is referred to as a software master. master mode is enabled by setting the i2cm bit in the i2ccon register. to transmit data on the sdata line, mde must be set to enable the output driver on the sdata pin. if mde is set, then the sdata pin will be pulled high or low depending on whether the mdo bit is set or cleared. mco controls the sclock pin and is always configured as an output in master mode. in master mode the sclock pin will be pulled high or low depending on the whether mco is set or cleared. to receive data, mde must be cleared to disable the output driver on sdata. software must provide the clocks by toggling the mco bit and read the sdata pin via the mdi bit. if mde is cleared mdi can be used to read the sdata pin. the value of the sdata pin is latched into mdi on a rising edge of sclock. mdi is set if the sdata pin was high on the last rising edge of sclock. mdi is cleared if the sdata pin was low on the last rising edge of sclock. software must control mdo, mco, and mde appropriately to generate the start condition, slave address, acknowledge bits, data bytes, and stop conditions appropriately. these functions are provided in technical note uc001. hardware slave mode after reset the aduc831 defaults to hardware slave mode. the i 2 c interface is enabled by clearing the spe bit in spicon. slave mode is enabled by clearing the i2cm bit in i2ccon. the aduc831 has a full hardware slave. in slave mode the i 2 c address is stored in the i2cadd register. data received or to be transmitted is stored in the i2cdat register. once enabled in i 2 c slave mode the slave controller waits for a start condition. if the aduc831 detects a valid start condi- tion, followed by a valid address, followed by the r/ w ici ti c i cieipsr eaiesr ; enabling i2c interrupts for the aduc831 mov ieip2,#01h ; enable i2c interrupt setb ea on the aduc831 an autoclear of the i2ci bit is implemented so this bit is cleared automatically on a read or write access to the i2cdat sfr. mov i2cdat, a ; i2ci auto cleared mov a, i2cdat ; i2ci auto cleared if for any reason the user tries to clear the interrupt more than once, i.e., access the data sfr more than once per interrupt then the i 2 c controller will halt. the interface will then have to be reset using the i2crs bit. the user can choose to poll the i2ci bit or enable the interrupt. in the case of the interrupt, the pc counter will vector to 003bh at the end of each complete byte. for the first byte when the user gets to the i2ci isr, the 7-bit address and the r/ w icdatsr tictr w i ict ticdat iict ts ict icdat oadc1 scocici t tici acinacnot tadc1 stop wstop )s nac ticrs i ct i) s tart
rev. 0 e42e aduc831 table xiii. dpcon sfr bit designations bit name description 7 ---- reserved for future use. 6 dpt data pointer automatic toggle enable. cleared by user to disable auto swapping of the dptr. set in user software to enable automatic toggling of the dptr after each movx or movc instruction. 5d p1m1 shadow data pointer mode. 4d p1m0 these two bits enable extra modes of the shadow data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the shadow data pointer 00 8052 behavior 01 dptr is post-incremented after a movx or a movc instruction. 10 dptr is post-decremented after a movx or movc instruction. 11 dptr lsb is toggled after a movx or movc instruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 3d p0m1 main data pointer mode. 2d p0m0 these two bits enable extra modes of the main data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the main data pointer 00 8052 behavior 01 dptr is post-incremented after a movx or a movc instruction. 10 dptr is post-decremented after a movx or movc instruction. 11 dptr lsb is toggled after a movx or movc instruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 1t his bit is not implemented to allow the inc dpcon instruction toggle the data pointer without incrementing the rest of the sfr. 0 dpsel data pointer select. cleared by user to select the main data pointer. this means that the contents of this 24-bit register is placed into the three sfrs dpl, dph, and dpp. set by the user to select the shadow data pointer. this means that the contents of a separate 24-bit register appears in the three sfrs dpl, dph, and dpp. dual data pointer the aduc831 incorporates two data pointers. the second data pointer is a shadow data pointer and is selected via the data pointer control sfr (dpcon). dpcon also includes some nice features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. dpcon is described in table xiii. dpcon data pointer control sfr sfr address a7h power-on default value 00h bit addressable no note 1: this is the only place where the main and shadow data pointers are distinguished. everywhere else in this data sheet wherever the dptr is mentioned, operation on the active dptr is implied. note 2: only movc/movx @dptr instructions are relevant above. movc/movx pc/@ri instructions will not cause the dptr to automatically post increment/decrement, and so on. to illustrate the operation of dpcon, the following code will copy 256 bytes of code memory at address d000h into xram starting from address 0000h. the following code uses 16 bytes and 2054 cycles. to perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented). mov dptr,#0 ; main dptr = 0 mov dpcon,#55h ; select shadow dptr ; dptr1 increment mode, ; dptr0 increment mode ; dptr auto toggling on mov dptr,#0d000h ; shadow dptr = d000h moveloop: clr a movc a,@a+dptr ; get data ; post inc dptr ; swap to main dptr (data) movx @dptr,a ; put acc in xram ; increment main dptr ; swap shadow dptr (code) mov a, dpl jnz moveloop
rev. 0 aduc831 e43e psmcon power supply monitor control register sfr address dfh power-on default value deh bit addressable no table xiv. psmcon sfr bit designations bit name description 7 ---- reserved. 6 cmpd dv dd comparator bit. this is a read-only bit and directly reflects the state of the dv dd comparator. read 1 indicates the dv dd supply is above its selected trip point. read 0 indicates the dv dd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. this bit will be set high by the microconverter if either cmpa or cmpd is low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cmpd and /or cmpa return (and remain) high, a 250 ms counter is started. when this counter times out, the psmi interrupt is cleared. psmi can also be written by the user. however, if either com parator output is low, it is not possible for the user to clear psmi. 4 tpd1 dv dd trip point selection bits. 3 tpd0 these bits select the dv dd trip point voltage as follows: tpd1 tpd0 selected dv dd trip point (v) 00 4.37 01 3.08 10 2.93 11 2.63 2 ---- reserved. 1 ---- reserved. 0 psmen power supply monitor enable bit. set to 1 by the user to enable the power supply monitor circuit. cleared to 0 by the user to disable the power supply monitor circuit. power supply monitor as its name suggests, the power supply monitor, once enabled, monitors the dv dd supply on the aduc831. it will indicate when any of the supply pins drops below one of four user- selectable voltage trip points, from 4.63 v to 4.39 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.7 v. monitor function is controlled via the psmcon sfr. if enabled via the ieip2 sfr, the monitor will interrupt the core using the psmi bit in the psmcon sfr. this bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms. this monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. the supply monitor is also protected against spurious glitches triggering the interrupt circuit.
rev. 0 e44e aduc831 wdcon watchdog timer control register sfr address c0h power-on default value 10h bit addressable yes table xv. wdcon sfr bit designations bit name description 7 pre3 watchdog timer prescale bits. 6 pre2 the watchdog timeout period is given by the equation: t wd = (2 pre clr ea ; disable interrupts while writing ;to wdt setb wdwr ;allow write to wdcon mov wdcon, #72h ;enable wdt for 2.0s timeout setb ea ;enable interrupts again (if rqd) watchdog timer the purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the aduc831 enters an erroneous state, possibly due to a program- ming error or electrical noise. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled, the watch- dog circuit will generate a system reset or interrupt (wds) if the user program fails to set the watchdog (wde) bit within a predetermined amount of time (see pre3e0 bits in wdcon). the watchdog timer itself is a 16-bit counter that is clocked at 32 khz by the internal r/c oscillator. the watchdog time out interval can be adjusted via the pre3e0 bits in wdcon. full control and status of the watchdog timer function can be con- trolled via the watchdog timer control sfr (wdcon). the wdcon sfr can only be written by user software if the double write sequence described in wdwr below is initiated on every write access to the wdcon sfr.
rev. 0 aduc831 e45e time interval counter (tic) a time interval counter is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. the tic is capable of timeout intervals ranging from 1/128 second to 255 hours. furthermore, this counter is clocked by an internal r/c oscillator rather than the external crystal and has the ab ility to remain active in power-down mode and time long power-down intervals. this has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. the r/c oscillator is accurate to +10% at 25?c. note: instructions to the tic sfrs are also clocked at 32 khz, sufficient time must be allowed for in user code for these instructions to execute. six sfrs are associated with the time interval counter, ti mecon being its control register. depending on the configuration of the it0 and it1 bits in timecon, the selected time counter regis- ter overflow will clock the interval counter. when this counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. if the aduc831 is in power-down mode, again with tic inter- rupt enabled, the tii bit w ill wake up the device and resume code execution by vectoring directly to the tic interrupt service vector address at 0053h. the tic-related sfrs are described below. note also that the time-base sfrs can be written initially with the current time, the tic can then be controlled and accessed by user software. in effect, this facilitates the imple- mentation of a real-time clock. a block diagram of the tic is shown in figure 35. timecon tic control register sfr address a1h power-on default value 00h bit addressable no table xvi. timecon sfr bit designations bit name description 7 ---- reserved for future use. 6 tfh twenty-four hour select bit. set by the user to enable the hour counter to count from 0 to 23. cleared by the user to enable the hour counter to count from 0 to 255. 5 its1 interval timebase selection bits. 4 its0 written by user to determine the interval counter update rate. its1 its0 interval timebase 00 1/128 second 01 seconds 10 minutes 11 hours 3 sti single time interval bit. set by user to generate a single interval timeout. if set, a timeout will clear the tien bit. cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 tii tic interrupt bit. set when the 8-bit interval counter matches the value in the intval sfr. cleared by user software. 1 tien time interval enable bit. set by user to enable the 8-bit time interval counter. cleared by user to disable the interval counter. 0 tcen time clock enable bit. set by user to enable the time clock to the time interval counters. cleared by user to disable the clock to the time interval counters and reset the time interval sfrs to the last value written to them by the user. the time registers (hthsec, sec, min, and hour) can be written while tcen is low. 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour tien interval timeout time interval counter interrupt 8-bit interval counter time interval intval interval timebase selection mux tcen 32khz internal r/c osc. its0, 1 compare count = intval? figure 35. tic, simplified block diagram
rev. 0 e46e aduc831 intval user time interval select register function user code writes the required time interval to this register. when the 8-bit interval counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. sfr address a6h power-on default value 00h bit addressable no valid value 0 to 255 decimal hthsec hundredths seconds time register function this register is incremented in 1/128 second intervals once tcen in timecon is active. the hthsec sfr counts from 0 to 127 before rolling over to increment the sec time register. sfr address a2h power-on default value 00h bit addressable no valid value 0 to 127 decimal sec seconds time register function this register is incremented in 1-second intervals once tcen in timecon is active. the sec sfr counts from 0 to 59 before rolling over to increment the min time register. sfr address a3h power-on default value 00h bit addressable no valid value 0 to 59 decimal min minutes time register function this register is incremented in 1-minute intervals once tcen in timecon is active. the min counts from 0 to 59 before rolling over to increment the hour time register. sfr address a4h power-on default value 00h bit addressable no valid value 0 to 59 decimal hour hours time register function this register is incremented in 1-hour intervals once tcen in timecon is active. the hour sfr counts from 0 to 23 before rolling over to 0. sfr address a5h power-on default value 00h bit addressable no valid value 0 to 23 decimal
rev. 0 aduc831 e47e 8052 compatible on-chip peripherals this section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. these remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 sfr bit definitions. parallel i/o the aduc831 uses four input/output ports to exchange data with external devices. in addition to performing general-purpose i/o, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general-purpose i/o pin. port 0 port 0 is an 8-bit, open-drain, bidirectional i/o port that is directly controlled via the port 0 sfr. port 0 is also the multiplexed low-order address and data bus during accesses to external pro- gram or data memory. figure 36 shows a typical bit latch and i/o buffer for a port 0 port pin. the bit latch (one bit in the port?s sfr) is represented as a type d flip-flop, which will clock in a value from the inter- nal bus in response to a write to latch signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a read latch signal from the cpu. the level of the port pin itself is placed on the internal bus in response to a read pin signal from the cpu. some instructions that read a port activate the read latch signal, and others activate the read pin signal. see the following read-modify-write instruc- tions section for more details. control read latch internal bus write to latch read pin d cl q q atc dv dd addrdata p0 pin p0io ap0 addraddrdata contro dp0sr1 1w contro addrdatat p0 iiop01 p0sr ip0 t nandcontro ete p0 p00 v o 1a p1 p1p1sr p1 p1 1p1 t 0 t tvii tvii p1ap p a p10 t2tc2ei p11 t2etc2crt p1 ss ssspii) read atc interna s write toatc read pin d c q atc p1 pin toadc p1io p2 p2 p2srp2 2 ap2 addraddrdata contro p0icontro1 addrp0sr p2sr
rev. 0 e48e aduc831 in general-purpose i/o port mode, port 2 pins that have 1s written to them are pulled high by the internal pull-ups (figure 39) and, in that state, they can be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 pins with 0s written to them will drive a logic low output voltage (v ol ) and will be capable of sinking 1.6 ma. p2.6 and p2.7 can also be used as pwm outputs. in the case that they are selected as the pwm outputs via the cfg831 sfr, the pwm outputs will overwrite anything written to p2.6 or p2.7. control read latch internal bus write to latch read pin d cl q q atc dv dd addr p2 pin dv dd interna pp seeireor detaisointernapp p2io q ro port atc 2c dea q1 dv dd q2 dv dd q dv dd p pin q ipc p p psrp1 ap p 0v o a p tviiitp psr1 o0 tviiipap p a p0 rdartipsdio0 p1 tdartop sco0 p2 int0 ei0) p int1 ei1)pw1iso p t0tc0ei) pwecpw0 p t1tc1ei) p wr edws) p rd edrs) pppwi pwc1sr pwpp read atc interna s write toatc read pin d c q atc dv dd p pin interna pp seeire ordetaiso internapp aternate otpt nction aternate inpt nction 0 pio adio ispii 2 c scocsdataosi tio 1spi 2i 2 c ni 2 cspe0et q1q2 spispe1etq1 spi ii 2 cspe0etqq 00 ispispe1 etq p0 p2 oscocs spi scocsdatai 2 c 0 nscocsdataosi sri 2 c tspii 2 c ardwarespi astersave q scitt trier q1 q2o dv dd scoc pin qo spe1spienae 1 scocpioe spi
rev. 0 aduc831 e49e mco i2cm sfr bits 50ns glitch rejection filter hardware i 2 c (slave only) q3 q4 sclock pin q2 q1 (off) dv dd spe = 0 (i 2 c e nable) figure 42. sclock pin i/o functional equivalent in i 2 c mode hardware spi (master/slave) q3 q1 q2 (off) dv dd sdata/ mosi pin q4 (off) spe = 1 (spi enable) figure 43. sdata/mosi pin i/o functional equivalent in spi mode q3 q4 q2 q1 (off) dv dd mdi mdo mde i2cm hardware i 2 c (slave only) 50ns glitch rejection filter sdata/ mosi pin sfr bits spe = 0 (i 2 c e nable) figure 44. sdata/mosi pin i/o functional equivalent in i 2 c mode miso is shared with p3.3 and as such has the same configuration as shown in figure 40. read-modify-write instructions some 8051 instructions that read a port read the latch, and others read the pin. the instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch. these are called read-modify- write instructions. listed below are the read-modify-write instructions. when the destination operand is a port, or a port bit, these instructions read the latch rather than the pin. anl (logical and, e.g., anl p1, a) orl (logical or, e.g., orl p2, a) xrl (logical ex-or, e.g., xrl p3, a) jbc (jump if bit = 1 and clear bit, e.g., jbc p1.1, label) cpl (complement bit, e.g., cpl p3.0) inc (increment, e.g., inc p2) dec (decrement, e.g., dec p2) djnz (decrement and jump if not zero, e.g., djnz p3, label) mov px.y, c * (move carry to bit y of port x) clr px.y * (clear bit y of port x) setb px.y * (set bit y of port x) the reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level of a pin. for example, a port pin might be used to drive the base of a transistor. when a 1 is written to the bit, the transistor is turned on. if the cpu then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a logic 0. reading the latch rather than the pin will return the correct value of 1. * these instructions read the port byte (all 8 bits), modify the addressed bit, and then write the new byte back to the latch.
rev. 0 e50e aduc831 user configuration and control of all timer operating modes is achieved via three sfrs: tmod, tcon control and configuration for timers 0 and 1. t2con control and configuration for timer 2. tmod timer/counter 0 and 1 mode register sfr address 89h power-on default value 00h bit addressable no table xix. tmod sfr bit designations bit name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while int1 tr1 ct1tr1 ct t1tcs st1) c) 1t 1s10) 0t 1s0 1 0 00 t1t1 01 1tct1t1 10 artct1 t1 11 tc1s t0c s0 int0 tr0 ct0tr0 ct t0tcs st0) c) 1 1t 0s1 0 0t 0s0 1 0 00 t0t0 01 1tct0t0 10 artct0 t0 11 t00 t0t1 tc tadc11tct0 t1tttc tc etct t01)a itt t s1 11 ict10 t0t1t isp w t sp1 s ) 101 t
rev. 0 aduc831 e51e tcon timer/counter 0 and 1 control register sfr address 88h power-on default value 00h bit addressable yes table xx. tcon sfr bit designations bit name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by user to turn on timer/counter 1. cleared by user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vectors to the interrupt service routine. 4 tr0 timer 0 run control bit. set by user to turn on timer/counter 0. cleared by user to turn off timer/counter 0. 3 ie1 * external interrupt 1 ( int1 ) sp int1 it1 cpc i it1 ei1ie1)tt s10) c) 1 ie0 ei0 int0 ) sp int0 it0 cpc i 0 it0 ei0ie0)tt s10) c) t01 int0 int1 tc01dr et 1 t0t0 t0 sraca t1t1 t1 srad
rev. 0 e52e aduc831 timer/counter 0 and 1 operating modes the following paragraphs describe the operating modes for timer/counters 0 and 1. unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. figure 45 shows mode 0 operation. int0 tr0 t0 t0 its t0 its interrpt c t 0 c t 1 tc00 i1 a10 t0tt0 t tr010 int0 1s1 int0 tr0 tcontodt1 t0 t0tt0 str0) 11tc) 10 11 int0 tr0 t0 t0 its t0 its interrpt c t 0 c t 1 tc01 2tca 2t0 o t0t0t0 t0tt0 contro t0 t0 its interrpt reoad t0 its int0 tr0 c t 0 c t 1 tc02 ttc t0t1t1 t tr10t0t0t0 t 0 t0t0cttr0 int0 t0t0 )tr1t1t1 tt0t1 wt0t1 baud rate generator . in fact, it can be used in any application not requiring an interrupt from timer 1 itself. control tf0 tl0 (8 bits) interrupt int0 tr0 c t 0 c t 1 core c12 t1 t0 its interrpt core c12 tr1 tc0
rev. 0 aduc831 e53e t2con timer/counter 2 control register sfr address c8h power-on default value 00h bit addressable yes table xxi. t2con sfr bit designations bit name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 will not be set when either rclk = 1 or tclk = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 rclk receive clock enable bit. set by user to enable the serial port to use t imer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the receive clock. 4 tclk transmit clock enable bit. set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by user to enable a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by user to start timer 2. cleared by user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by user to select counter function (input from external t2 pin). cleared by user to select timer function (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by user to enable captures on negative transitions at t2ex if exen2 = 1. cleared by user to enable auto-reloads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it. these are used as both timer data registers and timer capture/reload registers. th2 and tl2 timer 2, data high byte and low byte. sfr address = cdh, cch respectively. rcap2h and rcap2l timer 2, capture/reload byte and low byte. sfr address = cbh, cah respectively.
rev. 0 e54e aduc831 timer/counter operation modes the following paragraphs describe the operating modes for ti m er/ counter 2. the operating modes are selected by bits in the t2con sfr as shown in table xxii. table xxii. t2con operating modes rclk (or) tclk cap2 tr2 mode 00 1 16-bit autoreload 01 1 16-bit capture 1x 1b aud rate xx0 off 16-bit autoreload mode in autoreload mode, there are two options, which are selected by bit exen2 in t2con. if exen2 = 0, then when timer 2 rolls over it not only sets tf2, but also causes the timer 2 regis ters to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2. the autoreload mode is illustrated in figure 49. 16-bit capture mode in the capture mode, there are again two options, which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit tf2, the timer 2 overflow bit, which can be used to generate an inter- rupt. if exen2 = 1, then timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into regis- ters rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. the capture mode is illustrated in figure 50. the baud rate generator mode is selected by rclk = 1 and/or tclk = 1. in either case, if timer 2 is being used to generate the baud rate, the tf2 interrupt flag will not occur. therefore, timer 2 interrupts will not occur so they do not have to be disabled. in this mode the exf2 flag, however, can still cause interrupts and this can be used as a third external interrupt. baud rate generation will be described as part of the uart serial port operation in the following pages. core clk 12 t2 pin c/ t2 0 c t2 1 tr2 contro t2 its t2 its reoad t2 e2 tier interrpt een2 contro transition detector t2e pin rcap2 rcap2 tc21a t2 core c 12 t2 pin tr2 contro t2 its t2 its captre e2 tier interrpt een2 contro transition detector t2e pin rcap2 rcap2 c t2 0 c t2 1 0 tc21c
rev. 0 aduc831 e55e uart serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can com- mence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. the physical interface to the serial data network is via pins rxd(p3.0) and txd(p3.1), while the sfr interface to the uart is comprised of sbuf and scon, as described below. sbuf the serial port receive and transmit registers are both accessed through the sbuf sfr (sfr address = 99h). writing to sbuf loads the transmit register and reading sbuf accesses a physi- cally separate receive register. scon uart serial port control register sfr address 98h power-on default value 00h bit addressable yes table xxiii. scon sfr bit designations bit name description 7 sm0 uart serial mode select bits. 6 sm1 these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode 00 mode 0: shift register, fixed baud rate (core_clk/2) 01 mode 1: 8-bit uart, variable baud rate 10 mode 2: 9-bit uart, fixed baud rate (core_clk/64) or (core_clk/32) 11 mode 3: 9-bit uart, variable baud rate 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri will not be activated if a valid stop bit was not received. if sm2 is set, cleared, ri will be set as soon as the byte of data has been received. in modes 2 or 3, if sm2 is ri will not be activated if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri will be set as soon as the byte of data has been received. 4 ren serial port receive enable bit. set by user software to enable serial port reception. cleared by user software to disable serial port reception. 3t b8 serial port transmit (bit 9). the data loaded into tb8 will be the ninth data bit that will be transmitted in modes 2 and 3. 2 rb8 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched into rb8. for mode 1 the stop bit is latched into rb8. 1t i serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0r i serial port receive interrupt flag. set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software.
rev. 0 e56e aduc831 mode 0: 8-bit shift register mode mode 0 is selected by clearing both the sm0 and sm1 bits in the sfr scon. serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted or received. transmission is initiated by any instruction that writes to sbuf. the data is shifted out of the rxd line. the eight bits are transmitted with the least-significant bit (lsb) first, as shown in figure 51. core clk ale rxd (data out) txd (shift clock) data bit 0 data bit 1 data bit 6 data bit 7 s6 s5 s4 s3 s2 s1 s6 s5 s4 s4 s3 s2 s1 s6 s5 s4 s3 s2 s1 machine cycle 8 machine cycle 7 machine cycle 2 machine cycle 1 figure 51. uart serial port transmission, mode 0 reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0. when ri is cleared the data is cl ocked into the rxd line and the clock pulses are output from the txd line. mode 1: 8-bit uart, variable baud rate mode 1 is selected by clearing sm0 and setting sm1. each data byte (lsb first) is preceded by a start bit (0) and followed by a stop bit (1). therefore, 10 bits are transmitted on txd or received on rxd. the baud rate is set by the timer 1 or timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception). transmission is initiated by writing to sbuf. the write to sbuf signal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. the data is output bit by bit until the stop bit appears on txd and the transmit interrupt flag (ti) is automatically set as shown in figure 52. txd ti (s con.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i.e., ready for more data figure 52. uart serial port transmission, mode 0 reception is initiated when a 1-to-0 transition is detected on rxd. assuming a valid start bit was detected, character reception continues. the start bit is skipped and the eight data bits are clocked into the serial port shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth bit (stop bit) is clocked into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0, or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 2: 9-bit uart with fixed baud rate mode 2 is selected by setting sm0 and clearing sm1. in this mode the uart operates in 9-bit mode with a fixed baud rate. the baud rate is fixed at core_clk/64 by default, although by setting the smod bit in pcon, the frequency can be doubled to core_clk/32. eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). the ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. to transmit, the eight data bits must be written into sbuf. the ninth bit must be written to tb8 in scon. when trans- mission is initiated, the eight data bits (from sbuf) are loaded onto the transmit shift register (lsb first). the contents of tb8 are loaded into the ninth bit position of the transmit shift regis- ter. the transmission will start at the next valid baud rate clock. the ti flag is set as soon as the stop bit appears on txd. reception for mode 2 is similar to that of mode 1. the eight data bytes are input at rxd (lsb first) and loaded onto the receive shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth data bit is latched into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0, or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 3: 9-bit uart with variable baud rate mode 3 is selected by setting both sm0 and sm1. in this mode, the 8051 uart serial port operates in 9-bit mode with a vari- able baud rate determined by either timer 1 or timer 2. the operation of the 9-bit uart is the same as for mode 2 but the baud rate can be varied as for mode 1. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. uart serial port baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed: mode baud rate = (core clock frequency / ) 012 mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/64 of the core clock. if smod = 1, the baud rate is 1/32 of the core clock: mode baud rate = ( / ) core clock frequency) smod 2264 ( mode 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the overflow rate in timer 1 or timer 2, or both (one for transmit and the other for receive).
rev. 0 aduc831 e57e timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: modes and baud rate = (/ ) (timer overflow rate) smod 13 232 1 the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter opera- tion, and in any of its three running modes. in the most typical application, it is configured for timer operation in the autoreload mode (high nibble of tmod = 0010 binary). in that case, the baud rate is given by the formula: modes and baud rate = / core clock / ( ? th smod 13 ()( [ ])) 232 12 256 1 table xxiv shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 mhz and 12 mhz. generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. table xxiv. commonly-used baud rates, timer 1 core ideal clk smod th1-reload actual % baud (mhz) value value baud error 9600 12 1 e7 (f9h) 8929 7 19200 11.0592 1 e3 (fdh) 19200 0 9600 11.0592 0 e3 (fdh) 9600 0 2400 11.0592 0 e12 (f4h) 2400 0 timer 2 generated baud rates baud rates can also be generated using timer 2. using timer 2 is similar to using timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. because timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible using timer 2. modes and baud rate = ( / ) (timer overflow rate) 13 116 2 therefore, when timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. thus, it increments six times faster than timer 1, and therefore baud rates six times faster are possible. because timer 2 has 16-bit autoreload capability, very low baud rates are still possible. timer 2 is selected as the baud rate generator by setting the tclk and/or rclk in t2con. the baud rates for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer 2 into its baud rate generator mode as shown in figure 53. in this case, the baud rate is given by the formula: modes 1 and 3 baud rate = (core clk)/( ? rcap h, rcap l 32 65536 2 2 [( )]) table xxv shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 mhz and 12 mhz. table xxv. commonly used baud rates, timer 2 core ideal clk rcap2h rcap2l actual % baud (mhz) value value baud error 19200 12 e1 (ffh) e20 (ech) 19661 2.4 9600 12 e1 (ffh) e41 (d7h) 9591 0.1 2400 12 e1 (ffh) e164 (5ch) 2398 0.1 1200 12 e2 (feh) e72 (b8h) 1199 0.1 19200 11.0592 e1 (ffh) e18 (eeh) 19200 0 9600 11.0592 e1 (ffh) e36 (dch) 9600 0 2400 11.0592 e1 (ffh) e144 (70h) 2400 0 1200 11.0592 e2 (ffh) e32 (e0h) 1200 0 core clk 2 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin transition detector exf 2 timer 2 interrupt note: availability of additional external interrupt rcap2l rcap2h timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow c/ t2 0 c t2 1 noteoscreqisdivided2not12 t2artr
rev. 0 e58e aduc831 timer 3 generated baud rates the high integer dividers in a uart block mean that high speed baud rates are not always possible using some particular crystals. for example, using a 12 mhz crystal, a baud rate of 115200 is not possible. to address this problem, the aduc831 has added a dedicated baud rate timer (timer 3) specifically for generating highly accurate baud rates. timer 3 can be used instead of timer 1 or timer 2 for generating very accurate high speed uart baud rates including 115200 and 230400. timer 3 also allows a much wider range of baud rates to be obtained. in fact, every desired bit rate from 12 bit/s to 393216 bit/s can be generated to within an error of 0.8%. timer 3 also frees up the other three timers, allowing them to be used for different applications. a block diagram of timer 3 is shown in figure 54 below. (1 + t3fd/64) 2 t3 rx/tx clock core clk t3en rx clock tx clock timer 1/timer 2 rx clock (fig 53) fractional divider 0 0 1 1 timer 1/timer 2 tx clock (fig 53) 16 2 div figure 54. timer 3, uart baud rates two sfrs (t3con and t3fd) are used to control timer 3. t3con is the baud rate control sfr, allowing timer 3 to be used to set up the uart baud rate, and setting up the binary divider (div). table xxvi. t3con sfr bit designations bit name description 7 t3bauden t3uartbaud enable set to enable timer 3 to generate the baud rate. when set, pcon.7, t2con.4 and t2con.5 are ignored. cleared to let the baud rate be generated as per a standard 8052. 6 5 4 3 2 div2 binary divider factor. 1 div1 div2 div1 div0 bin divider 0 div0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 the appropriate value to write to the div2-1-0 bits can be calcu- lated using the following formula where f core is the crystal frequency: note: the div value must be rounded down. div f 32 baud rate core =
log log( ) 2 t3fd is the fractional divider ratio required to achieve the required baud rate. we can calculate the appropriate value for t3fd using the following formula. note: t3fd should be rounded to the nearest integer. tfd f baud rate core div 3 2 2 = once the values for div and t3fd are calculated the actual baud rate can be calculated using the following formula. actual baud rate = 2f 2 (t3fd+ 64) core div for example, to get a baud rate of 115200 while operating at 11.0592 mhz: div log log tfd h = () () == = () () == 11059200 32 115200 2 1 58 1 32 11059200 2 115200 64 32 20 1 //. /e therefore, the actual baud rate is 115200 bit/s. table xxvii. commonly used baud rates using timer 3 ideal % baud crystal div t3con t3fd error 230400 11.0592 0 80h 20h 0.0 115200 11.0592 1 81h 20h 0.0 57600 11.0592 2 82h 20h 0.0 38400 11.0592 3 83h 08h 0.0 19200 11.0592 4 84h 08h 0.0 9600 11.0592 5 85h 08h 0.0 230400 12 0 80h 28h 0.16 115200 12 1 81h 28h 0.16 57600 12 2 82h 28h 0.16 38400 12 3 83h 0eh 0.16 19200 12 4 84h 0eh 0.16 9600 12 5 85h 0eh 0.16 230400 14 0 80h 3ah 0.39 115200 14 1 81h 3ah 0.39 57600 14 2 82h 3ah 0.39 38400 14 3 83h 1bh 0.16 19200 14 4 84h 1bh 0.16 9600 14 5 85h 1bh 0.16 230400 16 1 81h 05h 0.64 115200 16 2 82h 05h 0.64 57600 16 3 83h 05h 0.64 38400 16 3 83h 28h 0.16 19200 16 4 84h 28h 0.16 9600 16 5 85h 28h 0.16
rev. 0 aduc831 e59e interrupt system the aduc831 provides a total of nine interrupt sources with two priority levels. the control and configuration of the interrupt system is carried out through three interrupt-related sfrs. ie interrupt enable register ip interrupt priority register ieip2 secondary interrupt enable register ie interrupt enable register sfr address a8h power-on default value 00h bit addressable yes table xxviii. ie sfr bit designations bit name description 7e aw ritten by user to enable 1 or disable 0 all interrupt sources 6 eadc written by user to enable 1 or disable 0 adc interrupt 5 et2 written by user to enable 1 or disable 0 timer 2 interrupt 4e sw ritten by user to enable 1 or disable 0 uart serial port interrupt 3 et1 written by user to enable 1 or disable 0 timer 1 interrupt 2 ex1 written by user to enable 1 or disable 0 external interrupt 1 1 et0 written by user to enable 1 or disable 0 timer 0 interrupt 0 ex0 written by user to enable 1 or disable 0 external interrupt 0 ip interrupt priority register sfr address b8h power-on default value 00h bit addressable yes table xxix. ip sfr bit designations bit name description 7 ---- reserved for future use 6 padc written by user to select adc interrupt priority (1 = high; 0 = low) 5 pt2 written by user to select timer 2 interrupt priority (1 = high; 0 = low) 4p sw ritten by user to select uart serial port interrupt priority (1 = high; 0 = low) 3 pt1 written by user to select timer 1 interrupt priority (1 = high; 0 = low) 2 px1 written by user to select external interrupt 1 priority (1 = high; 0 = low) 1 pt0 written by user to select timer 0 interrupt priority (1 = high; 0 = low) 0 px0 written by user to select external interrupt 0 priority (1 = high; 0 = low) ieip2 secondary interrupt enable register sfr address a9h power-on default value a0h bit addressable no table xxx. ieip2 sfr bit designations bit name description 7 ---- reserved for future use 6p ti priority for time interval interrupt 5 ppsm priority for power supply monitor interrupt 4p si priority for spi/i 2 c interrupt 3 ---- this bit must contain zero 2 eti written by user to enable 1 or disable 0 time interval counter interrupt 1 epsmi written by user to enable 1 or disable 0 power supply monitor interrupt 0 esi written by user to enable 1 or disable 0 spi/i 2 c serial port interrupt
rev. 0 e60e aduc831 interrupt priority the interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each interrupt. an interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. an interrupt cannot be interrupted by another interrupt of the same priority level. if two interrupts of the same priority level occur simultaneously, a polling sequence is observed as shown in table xxxi. table xxxi. priority within an interrupt level source priority description psmi 1 (highest) power supply monitor interrupt wds 2 watchdog timer interrupt ie0 2 external interrupt 0 adci 3 adc interrupt tf0 4 timer/counter 0 interrupt ie1 5 external interrupt 1 tf1 6 timer/counter 1 interrupt i2ci + ispi 7 spi interrupt ri + ti 8 serial interrupt tf2 + exf2 9 (lowest) timer/counter 2 interrupt tii 11 (lowest) time interval counter interrupt interrupt vectors when an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is l oaded into the program counter. the interrupt vector addresses are shown in table xxxii. table xxxii. interrupt vector addresses source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h tf2 + exf2 002bh adci 0033h i2ci + ispi 003bh psmi 0043h tii 0053h wds 005bh aduc831 hardware design considerations this section outlines some of the key hardware design consider- ations that must be addressed when integrating the aduc831 into any hardware system. clock oscillator the clock source for the aduc831 can come either from an external source or from the internal clock oscillator. to use the internal clock oscillator, connect a parallel resonant crystal between xtal1 and xtal2, and connect a capacitor from each pin to ground as shown below. xtal2 xtal1 to internal timng circuits aduc831 figure 55. external parallel resonant crystal connections xtal2 xtal1 to internal timng circuits aduc831 external clock source figure 56. connecting an external clock source whether using the internal oscillator or an external clock source, the aduc831?s specified operational clock speed range is 400 khz to 16 mhz. the core itself is static, and will function all the way down to dc. but at clock speeds slower that 400 khz the adc will no longer function correctly. therefore, to ensure specified o peration, use a clock frequency of at least 400 khz and no m ore than 16 mhz. note: the flash/ee memory may not program correctly at a clock frequency of less than 2 mhz. external memory interface in addition to its internal program and data memories, the aduc831 can access up to 64 kbytes of external program memory (rom/ prom/etc.) and up to 16 mbytes of external data memory (sram). to select from which code space (internal or external program memory) to begin executing instructions, tie the ea )w ea v dd )0 eew ea ) 0 a ea spe e) adc1n1io
rev. 0 aduc831 e61e (ports 0 and 2) are dedicated to bus functions during external program memory fetches. port 0 (p0) serves as a m ultiplexed address/data bus. it emits the low byte of the program counter (pcl) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. during the time that the low byte of the program counter is valid on p0, the sign al ale (address latch enable) clocks this byte into an address latch. meanwhile, port 2 (p2) emits the high byte of the pro gram c ounter (pch), then psen epro adc1 atc epro oe aa1 a0a d0d instrction adc1 psen p2 ae p0 epi n1 e p0p2 w p 0 2 io t rat01 c atc sra oe aa1 a0a d0d data adc1 rd p2 ae p0 we wr edi as ira adc11 ra atc adc1 rd p2 ae p0 wr atc sra oe aa1 a0a d0d data we a1a2 edi 1 as ip0p0 idp ae adc1 srap2p2 dppae dpip2 dppsra01 ps tadc12 v 2 va 2 v v 10 v 2 v v n01pqpcsp dv dd d nd av dd a nd ncsp sav dd dv dd av dd dv dd av dd dv dd 0v art av dd dv dd s 0 dv dd adc1 and av dd + 0.1 f 10 f analog supply 10 f dgnd 0.1 f digital supply + figure 60. external dual-supply connections
rev. 0 e62e aduc831 as an alternative to providing two separate power supplies, the user can help keep av dd quiet by placing a small series resistor and/or ferrite bead between it and dv dd , and then decoupling av dd separately to ground. an example of this configuration is shown in figure 61. with this configuration other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the av dd supply line as well. the user will still want to include back-to-back schottky diodes between av dd and dv dd in order to protect from power-up and power-down transient con- ditions that could separate the two supply voltages momentarily. dv dd aduc831 agnd av dd 0.1 f 10 f 10 f dgnd 0.1 f digital supply + bead 1.6v figure 61. external single-supply connections notice that in both figure 60 and figure 61, a large value (10 f) reservoir capacitor sits on dv dd and a separate 10 f capacitor sits on av dd . also, local small-value (0.1 f) capacitors are located at each v dd pin of the chip. as per standard design practice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, it should also be noted that, at all times, the analog and digital ground pins on the aduc831 must be referenced to the same system ground reference point. power consumption the currents consumed by the various sections of the aduc831 are shown in table xxxiii. the core values given represent the current drawn by dv dd , while the rest (adc, dac, voltage ref) are pulled by the av dd pin and can be disabled in software when not in use. the other on-chip peripherals (watchdog timer, power supply monitor, and so on) consume negligible current and are therefore lumped in with the core operating current here. of course, the user must add any currents sourced by the parallel and serial i/o pins, and that sourced by the dac, in order to determine the total current needed at the aduc831? supply pins. also, current drawn from the dv dd supply will increase by approximately 10 ma during flash/ee erase and program cycles. table xxxiii. typical i dd of core and peripherals v dd = 5 v v dd = 3 v core: (normal mode) (1.6 nas asserting the reset pin (pin 15) returns to normal mode. all registers are set to their default state a nd program execution starts at the reset vector once the res et pin is de-asserted. cycling power all registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. time interval counter (tic) interrupt power-down mode is terminated and the cpu services the tic interrupt. the reti at the end of the tic isr w ill return the core to the instruction after that which enabled power-down. i 2 c or spi interrupt power-down mode is terminated and the cpu services the i 2 c/spi interrupt. the reti at the end of the isr will return the core to the instruction after that which enabled power-down. it should be noted that the i 2 c/spi power down interrupt enable bit (seripd) in the pcon sfr must first be set to allow this mode of operation. int0 interrupt power-down mode is terminated and the cpu services the int0 tretiisr i int0 int0pd) pconsr por aporpor) adc1dv dd vpor adc1adv dd v 1 1w t v por adc11 v por
rev. 0 aduc831 ?3 128ms typ 1.0v typ 128ms typ 2.45v typ 1.0v typ internal core reset dv dd figure 62. internal por operation grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of aduc831-based designs in order to achieve optimum performance from the adc and dacs. although the aduc831 has separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are con- nected together very close to the aduc831, as illustrated in the simplified example of figure 63a. in systems where digital and analog ground planes are connected together somewhere else (at the system? power supply for example), they cannot be con- nected again near the aduc831 since a ground loop would result. in these cases, tie the aduc831? agnd and dgnd pins all to the analog ground plane, as illustrated in figure 63b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. the aduc831 can then be placed between the digital and analog sections, as illustrated in figure 63c. in all of these scenarios, and in more complicated real-life applica- tions, keep in mind the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their desti- nations. for example, do not power components on the analog side of figure 63b with dv dd since that would force return currents from dv dd to flow through agnd. also, try to avoid digital currents flowing under an alog circuitry, wh ich could happen if the user placed a noisy digital chip on the left half of the board in figure 63c. whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. and of course, make all connections to the ground plane directly, w ith little or no trace separating the pin from its via to ground. note that the bottom paddle of the csp package should not be connected to ground. it should be left unconnected. if the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the aduc831? digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the aduc831 input pins. a value of 100 ? or 200 ? is usually suffi- cient to prevent high speed signals from coupling capacitively into the aduc831 and affecting the accuracy of adc conversions. dgnd agnd pl ace analog comp onents here pl ace digital comp onents here gnd pl ace analog comp onents here pl ace digital comp onents here dgnd a. agnd pl ace analog comp onents here pl ace digital comp onents here b. c. figure 63. system grounding schemes other hardware considerations to facilitate in-circuit programming, plus in-circuit debug and emulation options, use rs will want to implement some simple co nn ection points in their hardware that will allow easy access to download, debug, and emulation modes. in-circuit serial download access nearly all aduc831 designs will want to take advantage of the in-circuit reprogrammability of the chip. this is accomplished by a connection to the aduc831? uart, which requires an exter- na l rs-232 chip for level translation if downloading code from a pc. basic configuration of an rs-232 connection is illustrated in figure 66 with a simple adm202-based circuit. if users would rather not design an rs-232 chip onto a board, refer to the application note ?c006? 4-wire uart-to-pc interface * for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the aduc831. in addition to the basic uart connections, users will also need a way to trigger the chip into download mode. this is accom- plished via a 1 k ? pull-down resistor that can be jumpered onto the psen pin, as shown in figure 64. to get the aduc831 into download mode, simply connect this jumper and power-cycle the device (or manually reset the device, if a manual reset button is avail able) and it will be ready to receive a new program serially. with the jum per removed, the device will come up in normal mode (and run the program) whenever power is cycled or reset is toggled. * application note uc006 is available at www.analog.com/microconverter
rev. 0 e64e aduc831 c1+ v+ c1e c2+ c2e ve t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm202 1 2 3 4 5 6 7 8 9 dv dd 9-pin d-sub female dv dd 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 dv dd 1k dv dd 1k 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 11.0592mhz dv dd av dd av dd agnd c ref v ref dac0 dac1 dv dd dgnd psen ea dnd dv dd ta2 ta1 reset rd td dv dd dnd notconnectedintiseape adc1 adc0 adc anaoinpt vreotpt dacotpt eadc1spqpp n psen e i) reset )n psen t psen psen espd i nadc1 ro) spe aadc1 ice) adc1i ea n t ea 1 t t a )01 ) 01 a ) tsc aadc1i
rev. 0 aduc831 e65e development tools there are two models of development tools available for the aduc831, namely: quickstart?entry-level development system quickstart plus?comprehensive development system these systems are described briefly below. quickstart development system the quickstart development system is an entry-level, low cost development tool suite supporting the aduc831. the system consists of the following pc-based (windows compatible) h ard ware and software development tools. hardware: aduc831 evaluation board and serial port p rogramming cable. software: aspire integrated development environment. incorporates 8051 assembler and serial port debugger. serial download software. miscellaneous: cd-rom documentation and prototype device. figure 65 shows the typical components of a quickstart devel opment system. a brief description of some of the software tools components in the quickstart development system follows. figure 65. components of the quickstar development system figure 66. typical debug session download?in-circuit serial downloader the serial downloader is a w indows application th at allows th e user to serially download an assembled program (intel hex format file) to the on-chip program flash memory via the serial com1 port on a standard pc. an application note (uc004) detailing this serial download protocol is available from www.analog.com/microconverter. aspire?ide the aspire integrated development environment is a windows application that allows the user to compile, edit, and debug code in the same environment. the aspire software allows users to debug code execution on silicon using the microconverter uart serial port. the debugger provides access to all on-chip periph erals during a typical debug session as well as single-step, animate, and break-point code execution control. note, the aspire ide software is also included as part of the quickstart plus system. as part of the quickstart plus system, the aspire ide also supports mixed level and c source debug. this is not available in the q uickstart system, but there is an example project that demonstrates this capability. quickstart plus development system the quickstart plus development system offers users enhanced nonintrusive debug and emulation tools. the system consists of the following pc based (windows compatible) hardware and software development tools. hardware: aduc831 p rototype board accutron nonintrusive single pin emulator software: aspire integrated development environment. features full ?c? and assembly emulation using the accutron single pin emulator. miscellaneous: cd-rom documentation. figure 67. accutron single pin emulator windows is a registered trademark of microsoft corporation.
rev. 0 e66e aduc831 timing specifications 1, 2, 3 (av dd = dv dd = 3.0 v or 5.0 v 10 %. all specifications t a = t min to t max , unless otherwise noted.) 12 mhz variable clock parameter min typ max min typ max unit figure clock input (external clock driven xtal1) t ck xtal1 period 83.33 62.5 1000 ns 68 t ckl xtal1 width low 20 20 ns 68 t ckh xtal1 width high 20 20 ns 68 t ckr xtal1 rise time 20 20 ns 68 t ckf xtal1 fall time 20 20 ns 68 t cyc 4 aduc831 machine cycle time 1 12t ck s notes 1 ac inputs during testing are driven at dv dd e 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ih min for a logic 1 and v il max for a logic 0. 2 for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs. 3 c load for port0, ale, psen 100c oad 0 adc1ctcin1 c c c c cr ta1i dv dd 0v 0v 0dv dd 0v testpoints 0dv dd 01v v oad 01v v oad v oad 01v tiin reerence points v oad 01v v oad v oad 01v twc
rev. 0 aduc831 e67e 12 mhz variable clock parameter min max min max unit figure external program memory read cycle t lhll ale pulsewidth 127 2t ck e40 ns 70 t avll address valid to ale low 43 t ck e40 ns 70 t llax address hold after ale low 53 t ck e30 ns 70 t lliv ale low to valid instruction in 234 4t ck e 100 ns 70 t llpl ale low to psen c 0 0 pp psen p 0 c 0 piv psen vii 1 c 10 0 pi ii psen 00 0 pi ii psen c 0 aviv avii 1 c 10 0 pa psen a 0 pa a psen 0 0 0 av pc ot) instrction in) pc c aeo) psen o port0io port2o p a pa pi pi piv iv pp pa aviv 0 eprc
rev. 0 e68e aduc831 12 mhz variable clock parameter min max min max unit figure external data memory read cycle t rlrh rd p 00 c 100 1 av avae c 0 1 a aae c 1 rdv rd vdi c 1 1 rd da rd 00 1 rd d rd c 0 1 dv aevdi 1 c 10 1 avdv avdi c 1 1 w ae rd wr 00 00 c 0 c 0 1 avw av rd wr 0 c 10 1 ra rd a 0 0 1 w rd wr ae 1 c 0 c 100 1 a datain) c aeo) psen o port0io port2o rd o ) t lldv t llwl t avwl t avll t avdv t rlaz t rldv t rhdx t rhdz t whlh a0?7 (out) a16?23 a8?15 t rlrh figure 71. external data memory read cycle
rev. 0 aduc831 e69e 12 mhz variable clock parameter min max min max unit figure external data memory write cycle t wlwh wr p 00 c 100 av avae c 0 a aae c w ae rd wr 00 00 c 0 c 0 avw av rd wr 0 c 10 vw dv wr t c 0 vw ds wr c 10 w da wr c 0 w rd wr ae 1 c 0 c 100 a data c aeo) psen o port2o w avw av qvw wq w a0a a1a2 aa1 ww qvw wr o 2 edwc
rev. 0 e70e aduc831 12 mhz variable clock parameter min typ max min typ max unit figure uart timing (shift register mode) t xlxl serial port clock cycle time 1.0 12t ck s73 t qvxh output data setup to clock 700 10t ck e 133 ns 73 t dvxh input data setup to clock 300 2t ck + 133 ns 73 t xhdx input data hold after clock 0 0 ns 73 t xhqx output data hold after clock 50 2t ck e 117 ns 73 set ri or set ti 0 bit 1 t xlxl ale (o) txd (output clock) rxd (output data) rxd (input data) 1 bit 6 msb msb bit 6 bit 1 lsb t xhqx t qvxh t dvxh t xhdx 6 7 lsb figure 73. uart timing in shift register mode
rev. 0 aduc831 e71e parameter min max unit figure i 2 c compatible interface timing t l sclock low pulsewidth 4.7 s74 t h sclock high pulsewidth 4.0 s74 t shd start condition hold time 0.6 s74 t dsu data setup time 100 s74 t dhd data hold time 0.9 s74 t rsu setup time for repeated start 0.6 s74 t psu stop condition setup time 0.6 s74 t buf bus free time between a stop 1.3 s74 condition and a start condition t r rise time of both sclock and sdata 300 ns 74 t f fall time of both sclock and sdata 300 ns 74 t sup * pulsewidth of spike suppressed 50 ns 74 * input filtering on both the sclock and sdata inputs suppresses noise spikes less than 50 ns. msb t buf sdata (i/o) sclk (i) stop condition start condition repeated start lsb ack msb 12-78 9 1 s(r) ps t psu t dsu t shd t dhd t sup t dsu t dhd t h t sup t l t rsu t r t r t f t f figure 74. i 2 c compatible interface timing
rev. 0 e72e aduc831 parameter min typ max unit figure spi master mode timing (cpha = 1) t sl sclock low pulsewidth 330 ns 75 t sh sclock high pulsewidth 330 ns 75 t dav data output valid after sclock edge 50 ns 75 t dsu data input setup time before sclock edge 100 ns 75 t dhd data input hold time after sclock edge 100 ns 75 t df data output fall time 10 25 ns 75 t dr data output rise time 10 25 ns 75 t sr sclock rise time 10 25 ns 75 t sf sclock fall time 10 25 ns 75 sclock (cp ol = 0) t dsu sclock (cp ol = 1) mosi miso msb lsb lsb in bits 6e1 bits 6e1 t dhd t dr t dav t df t sh t sl t sr t sf msb in figure 75. spi master mode timing (cpha = 1)
rev. 0 aduc831 e73e parameter min typ max unit figure spi master mode timing (cpha = 0) t sl sclock low pulsewidth 330 ns 76 t sh sclock high pulsewidth 330 ns 76 t dav data output valid after sclock edge 50 ns 76 t dosu data output setup before sclock edge 150 ns 76 t dsu data input setup time before sclock edge 100 ns 76 t dhd data input hold time after sclock edge 100 ns 76 t df data output fall time 10 25 ns 76 t dr data output rise time 10 25 ns 76 t sr sclock rise time 10 25 ns 76 t sf sclock fall time 10 25 ns 76 sclock (cp ol = 0) t dsu sclock (cp ol = 1) mosi miso msb lsb lsb in bits 6e1 bits 6e1 t dhd t dr t dav t df t dosu t sh t sl t sr t sf msb in figure 76. spi master mode timing (cpha = 0)
rev. 0 e74e aduc831 parameter min typ max unit figure spi slave mode timing (cpha = 1) t ss ss scoce 0 s scocp 0 s scocp 0 dav dovscoce 0 ds distscoce 100 dd ditscoce 100 d dot 10 dr dort 10 sr scocrt 10 s scoct 10 ss ss scoce 0 iso osi scoc cp o1) scoc cp o0) ss s its1 s its1 sin dd ds dr d dav s s sr s ss sin ss spistcpa1
rev. 0 aduc831 e75e parameter min typ max unit figure spi slave mode timing (cpha = 0) t ss ss scoce 0 s scocp 0 s scocp 0 dav dovscoce 0 ds distscoce 100 dd ditscoce 100 d dot 10 dr dort 10 sr scocrt 10 s scoct 10 doss dov ss e 0 ss ss scoce 0 iso osi scoc cp o1) scoc cp o0) ss s its1 s its1 sin dd ds dr d dav doss s s sr s ss sin ss spistcpa0
rev. 0 c02986e0e11/02(0) printed in u.s.a. e76e aduc831 outline dimensions 52-lead plastic quad flatpack [mqfp] (s-52) dimensions shown in millimeters seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 14.15 13.90 sq 13.65 7.80 ref 10.20 10.00 sq 9.80 0.38 0.22 view a rotated 90 ccw 7 0 2.10 2.00 1.95 0.10 min coplanarity compliant to jedec standards mo-112-ac-1 56-lead frame chip scale package [lfcsp] 8 8 mm body (cp-56) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 bottom view 6.25 6.10 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 6.50 ref seating plane 0.10 max 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vlld-2 coplanarity 0.08

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